temp2222.rpt
来自「vhd语言」· RPT 代码 · 共 1,147 行 · 第 1/4 页
RPT
1,147 行
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\computer\alu\temp2222.rpt
temp2222
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - 24 OUTPUT 0 1 0 0 ADR1
28 - - C -- OUTPUT 0 1 0 0 ADR2
36 - - - 07 OUTPUT 0 1 0 0 ADR3
30 - - C -- OUTPUT 0 1 0 0 ADR4
22 - - B -- OUTPUT 0 1 0 0 ADR5
80 - - - 23 OUTPUT 0 1 0 0 ADR6
78 - - - 24 OUTPUT 0 1 0 0 ADR7
71 - - A -- OUTPUT 0 1 0 0 ADR8
23 - - B -- TRI 0 1 0 3 D1
67 - - B -- TRI 0 1 0 3 D2
61 - - C -- TRI 0 1 0 3 D3
65 - - B -- TRI 0 1 0 3 D4
25 - - B -- TRI 0 1 0 3 D5
21 - - B -- TRI 0 1 0 3 D6
24 - - B -- TRI 0 1 0 3 D7
66 - - B -- TRI 0 1 0 3 D8
37 - - - 09 OUTPUT 0 1 0 0 P1
64 - - B -- OUTPUT 0 1 0 0 P2
38 - - - 10 OUTPUT 0 1 0 0 P3
27 - - C -- OUTPUT 0 1 0 0 P4
19 - - A -- OUTPUT 0 1 0 0 P5
9 - - - 02 OUTPUT 0 1 0 0 P6
10 - - - 01 OUTPUT 0 1 0 0 P7
17 - - A -- OUTPUT 0 1 0 0 P8
58 - - C -- OUTPUT 0 1 0 0 Q1
60 - - C -- OUTPUT 0 1 0 0 Q2
51 - - - 18 OUTPUT 0 1 0 0 Q3
50 - - - 17 OUTPUT 0 1 0 0 Q4
6 - - - 04 OUTPUT 0 1 0 0 Q5
8 - - - 03 OUTPUT 0 1 0 0 Q6
7 - - - 03 OUTPUT 0 1 0 0 Q7
18 - - A -- OUTPUT 0 1 0 0 Q8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\computer\alu\temp2222.rpt
temp2222
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 04 DFFE + 1 2 1 3 |cdu:16|cdu16:20|74163:1|f74163:sub|QA (|cdu:16|cdu16:20|74163:1|f74163:sub|:34)
- 6 - B 04 DFFE + 1 2 1 2 |cdu:16|cdu16:20|74163:1|f74163:sub|QB (|cdu:16|cdu16:20|74163:1|f74163:sub|:111)
- 4 - B 04 AND2 0 4 0 2 |cdu:16|cdu16:20|74163:1|f74163:sub|:119
- 8 - B 04 DFFE + 1 1 1 2 |cdu:16|cdu16:20|74163:1|f74163:sub|QC (|cdu:16|cdu16:20|74163:1|f74163:sub|:122)
- 5 - B 04 DFFE + 1 2 1 1 |cdu:16|cdu16:20|74163:1|f74163:sub|QD (|cdu:16|cdu16:20|74163:1|f74163:sub|:134)
- 7 - B 17 DFFE + 2 0 1 4 |cdu:16|cdu16:22|74163:1|f74163:sub|QA (|cdu:16|cdu16:22|74163:1|f74163:sub|:34)
- 8 - B 17 AND2 1 2 0 1 |cdu:16|cdu16:22|74163:1|f74163:sub|:106
- 4 - B 17 DFFE + 2 1 1 3 |cdu:16|cdu16:22|74163:1|f74163:sub|QB (|cdu:16|cdu16:22|74163:1|f74163:sub|:111)
- 2 - B 17 AND2 1 3 0 4 |cdu:16|cdu16:22|74163:1|f74163:sub|:117
- 5 - B 17 DFFE + 2 1 1 2 |cdu:16|cdu16:22|74163:1|f74163:sub|QC (|cdu:16|cdu16:22|74163:1|f74163:sub|:122)
- 7 - B 04 AND2 0 2 0 1 |cdu:16|cdu16:22|74163:1|f74163:sub|:128
- 3 - B 17 DFFE + 2 1 1 4 |cdu:16|cdu16:22|74163:1|f74163:sub|QD (|cdu:16|cdu16:22|74163:1|f74163:sub|:134)
- - 3 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_0
- - 1 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_1
- - 5 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_2
- - 6 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_3
- - 7 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_4
- - 2 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_5
- - 4 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_6
- - 8 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:3|altram:sram|segment0_7
- 1 - B 05 AND2 2 0 0 8 |LPM_RAM_IO:3|:91
- 1 - C 24 AND2 2 0 0 8 :11
- 5 - B 09 AND2 2 0 0 8 :12
- 7 - B 01 DFFE 1 3 1 3 |74161:4|f74161:sub|QA (|74161:4|f74161:sub|:9)
- 5 - B 01 AND2 0 2 0 1 |74161:4|f74161:sub|:80
- 2 - B 01 AND2 0 3 0 2 |74161:4|f74161:sub|:84
- 8 - B 01 DFFE 1 3 1 2 |74161:4|f74161:sub|QB (|74161:4|f74161:sub|:87)
- 4 - B 01 AND2 0 2 0 1 |74161:4|f74161:sub|:94
- 1 - B 01 DFFE 1 3 1 2 |74161:4|f74161:sub|QC (|74161:4|f74161:sub|:99)
- 3 - B 01 DFFE 1 3 1 1 |74161:4|f74161:sub|QD (|74161:4|f74161:sub|:110)
- 3 - B 09 DFFE 1 2 1 5 |74161:5|f74161:sub|QA (|74161:5|f74161:sub|:9)
- 4 - B 09 AND2 0 2 0 1 |74161:5|f74161:sub|:84
- 7 - B 09 DFFE 1 3 1 4 |74161:5|f74161:sub|QB (|74161:5|f74161:sub|:87)
- 6 - B 09 AND2 0 3 0 1 |74161:5|f74161:sub|:94
- 2 - B 09 DFFE 1 3 0 3 |74161:5|f74161:sub|QC (|74161:5|f74161:sub|:99)
- 1 - B 09 AND2 0 4 1 3 |74161:5|f74161:sub|:104
- 8 - B 09 DFFE 1 3 1 2 |74161:5|f74161:sub|QD (|74161:5|f74161:sub|:110)
- 1 - B 07 OR2 3 0 0 0 |74244:14|~1~1~2
- 7 - B 05 OR2 s 2 2 0 1 |74244:14|~1~1~3~2
- 4 - B 05 OR2 1 2 1 0 |74244:14|~1~1~3
- 6 - B 17 OR2 s 2 2 0 1 |74244:14|~6~1~3~2
- 1 - B 17 OR2 1 2 1 0 |74244:14|~6~1~3
- 5 - B 05 OR2 s 2 2 0 1 |74244:14|~10~1~3~2
- 3 - B 05 OR2 1 2 1 0 |74244:14|~10~1~3
- 6 - B 07 OR2 s 2 2 0 1 |74244:14|~11~1~3~2
- 5 - B 07 OR2 1 2 1 0 |74244:14|~11~1~3
- 2 - B 07 OR2 s 2 2 0 1 |74244:14|~26~1~3~2
- 3 - B 07 OR2 1 2 1 0 |74244:14|~26~1~3
- 2 - B 05 OR2 s 2 2 0 1 |74244:14|~27~1~3~2
- 6 - B 05 OR2 1 2 1 0 |74244:14|~27~1~3
- 3 - B 04 OR2 s 2 2 0 1 |74244:14|~31~1~3~2
- 1 - B 04 OR2 1 2 1 0 |74244:14|~31~1~3
- 4 - B 07 OR2 s 2 2 0 1 |74244:14|~36~1~3~2
- 8 - B 07 OR2 1 2 1 0 |74244:14|~36~1~3
- 8 - B 23 DFFE 0 2 0 1 |74273:13|Q8 (|74273:13|:12)
- 5 - B 23 DFFE 0 2 0 1 |74273:13|Q7 (|74273:13|:13)
- 7 - B 23 DFFE 0 2 0 1 |74273:13|Q6 (|74273:13|:14)
- 7 - B 08 DFFE 0 2 0 1 |74273:13|Q5 (|74273:13|:15)
- 8 - B 08 DFFE 0 2 0 1 |74273:13|Q4 (|74273:13|:16)
- 4 - B 08 DFFE 0 2 0 1 |74273:13|Q3 (|74273:13|:17)
- 5 - B 08 DFFE 0 2 0 1 |74273:13|Q2 (|74273:13|:18)
- 2 - B 23 DFFE 0 2 0 1 |74273:13|Q1 (|74273:13|:19)
- 3 - B 23 LCELL 0 1 1 8 |74373:2|:12
- 2 - B 08 LCELL 0 1 1 8 |74373:2|:13
- 3 - B 08 LCELL 0 1 1 8 |74373:2|:14
- 6 - B 08 LCELL 0 1 1 8 |74373:2|:15
- 1 - B 08 LCELL 0 1 1 8 |74373:2|:16
- 1 - B 23 LCELL 0 1 1 8 |74373:2|:17
- 6 - B 23 LCELL 0 1 1 8 |74373:2|:18
- 4 - B 23 LCELL 0 1 1 8 |74373:2|:19
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\computer\alu\temp2222.rpt
temp2222
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 3/ 48( 6%) 1/ 48( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 33/ 96( 34%) 21/ 48( 43%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 7/16( 43%)
C: 4/ 96( 4%) 3/ 48( 6%) 2/ 48( 4%) 2/16( 12%) 5/16( 31%) 1/16( 6%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\computer\alu\temp2222.rpt
temp2222
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK-CDU
LCELL 8 :11
LCELL 8 :12
Device-Specific Information: d:\computer\alu\temp2222.rpt
temp2222
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 161CLRN
Device-Specific Information: d:\computer\alu\temp2222.rpt
temp2222
** EQUATIONS **
CLK-CDU : INPUT;
CLRN : INPUT;
EN : INPUT;
LDAR : INPUT;
PC : INPUT;
PC-BUS : INPUT;
RD : INPUT;
SW-BUS : INPUT;
T2 : INPUT;
T3 : INPUT;
WE : INPUT;
161CLRN : INPUT;
161LDN : INPUT;
-- Node name is 'ADR1'
-- Equation name is 'ADR1', type is output
ADR1 = _LC3_B23;
-- Node name is 'ADR2'
-- Equation name is 'ADR2', type is output
ADR2 = _LC2_B8;
-- Node name is 'ADR3'
-- Equation name is 'ADR3', type is output
ADR3 = _LC3_B8;
-- Node name is 'ADR4'
-- Equation name is 'ADR4', type is output
ADR4 = _LC6_B8;
-- Node name is 'ADR5'
-- Equation name is 'ADR5', type is output
ADR5 = _LC1_B8;
-- Node name is 'ADR6'
-- Equation name is 'ADR6', type is output
ADR6 = _LC1_B23;
-- Node name is 'ADR7'
-- Equation name is 'ADR7', type is output
ADR7 = _LC6_B23;
-- Node name is 'ADR8'
-- Equation name is 'ADR8', type is output
ADR8 = _LC4_B23;
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC4_B5, _LC1_B7);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(_LC1_B17, _LC1_B7);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(_LC3_B5, _LC1_B7);
-- Node name is 'D4'
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?