mulx6.rpt
来自「vhd语言」· RPT 代码 · 共 686 行 · 第 1/2 页
RPT
686 行
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zhuhui\mycpu\xianshi\mulx6.rpt
mulx6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 CLK
Device-Specific Information: d:\zhuhui\mycpu\xianshi\mulx6.rpt
mulx6
** EQUATIONS **
CLK : INPUT;
FIVE0 : INPUT;
FIVE1 : INPUT;
FIVE2 : INPUT;
FIVE3 : INPUT;
FOUR0 : INPUT;
FOUR1 : INPUT;
FOUR2 : INPUT;
FOUR3 : INPUT;
ONE0 : INPUT;
ONE1 : INPUT;
ONE2 : INPUT;
ONE3 : INPUT;
SIX0 : INPUT;
SIX1 : INPUT;
SIX2 : INPUT;
SIX3 : INPUT;
THREE0 : INPUT;
THREE1 : INPUT;
THREE2 : INPUT;
THREE3 : INPUT;
TWO0 : INPUT;
TWO1 : INPUT;
TWO2 : INPUT;
TWO3 : INPUT;
-- Node name is 'L0' from file "mulx6.tdf" line 31, column 7
-- Equation name is 'L0', type is output
L0 = !SS~6;
-- Node name is 'L1' from file "mulx6.tdf" line 31, column 7
-- Equation name is 'L1', type is output
L1 = SS~5;
-- Node name is 'L2' from file "mulx6.tdf" line 31, column 7
-- Equation name is 'L2', type is output
L2 = SS~4;
-- Node name is 'L3' from file "mulx6.tdf" line 31, column 7
-- Equation name is 'L3', type is output
L3 = SS~3;
-- Node name is 'L4' from file "mulx6.tdf" line 31, column 7
-- Equation name is 'L4', type is output
L4 = SS~2;
-- Node name is 'L5' from file "mulx6.tdf" line 31, column 7
-- Equation name is 'L5', type is output
L5 = SS~1;
-- Node name is 'OUT0' from file "mulx6.tdf" line 32, column 9
-- Equation name is 'OUT0', type is output
OUT0 = _LC4_B5;
-- Node name is 'OUT1' from file "mulx6.tdf" line 32, column 9
-- Equation name is 'OUT1', type is output
OUT1 = _LC8_B5;
-- Node name is 'OUT2' from file "mulx6.tdf" line 32, column 9
-- Equation name is 'OUT2', type is output
OUT2 = _LC1_A5;
-- Node name is 'OUT3' from file "mulx6.tdf" line 32, column 9
-- Equation name is 'OUT3', type is output
OUT3 = _LC3_A5;
-- Node name is 'SS~1' from file "mulx6.tdf" line 5, column 10
-- Equation name is 'SS~1', location is LC6_A5, type is buried.
SS~1 = DFFE( SS~2, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'SS~2' from file "mulx6.tdf" line 5, column 10
-- Equation name is 'SS~2', location is LC2_A5, type is buried.
SS~2 = DFFE( SS~3, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'SS~3' from file "mulx6.tdf" line 5, column 10
-- Equation name is 'SS~3', location is LC2_A10, type is buried.
SS~3 = DFFE( SS~4, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'SS~4' from file "mulx6.tdf" line 5, column 10
-- Equation name is 'SS~4', location is LC8_A10, type is buried.
SS~4 = DFFE( SS~5, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'SS~5' from file "mulx6.tdf" line 5, column 10
-- Equation name is 'SS~5', location is LC4_A10, type is buried.
SS~5 = DFFE(!SS~6, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'SS~6' from file "mulx6.tdf" line 5, column 10
-- Equation name is 'SS~6', location is LC6_B5, type is buried.
SS~6 = DFFE(!SS~1, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '~122~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~122~1', location is LC1_B5, type is buried.
-- synthesized logic cell
_LC1_B5 = LCELL( _EQ001);
_EQ001 = SS~4 & THREE0
# SS~5 & TWO0;
-- Node name is '~122~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~122~2', location is LC2_B5, type is buried.
-- synthesized logic cell
_LC2_B5 = LCELL( _EQ002);
_EQ002 = FIVE0 & SS~2
# FOUR0 & SS~3;
-- Node name is '~122~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~122~3', location is LC3_B5, type is buried.
-- synthesized logic cell
_LC3_B5 = LCELL( _EQ003);
_EQ003 = ONE0 & !SS~6
# SIX0 & SS~1;
-- Node name is ':122' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = LCELL( _EQ004);
_EQ004 = _LC1_B5
# _LC2_B5
# _LC3_B5;
-- Node name is '~124~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~124~1', location is LC1_A10, type is buried.
-- synthesized logic cell
_LC1_A10 = LCELL( _EQ005);
_EQ005 = SS~4 & THREE1
# SS~5 & TWO1;
-- Node name is '~124~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~124~2', location is LC5_B5, type is buried.
-- synthesized logic cell
_LC5_B5 = LCELL( _EQ006);
_EQ006 = FIVE1 & SS~2
# FOUR1 & SS~3;
-- Node name is '~124~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~124~3', location is LC7_B5, type is buried.
-- synthesized logic cell
_LC7_B5 = LCELL( _EQ007);
_EQ007 = ONE1 & !SS~6
# SIX1 & SS~1;
-- Node name is ':124' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC8_B5', type is buried
_LC8_B5 = LCELL( _EQ008);
_EQ008 = _LC1_A10
# _LC5_B5
# _LC7_B5;
-- Node name is '~126~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~126~1', location is LC6_A10, type is buried.
-- synthesized logic cell
_LC6_A10 = LCELL( _EQ009);
_EQ009 = SS~4 & THREE2
# SS~5 & TWO2;
-- Node name is '~126~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~126~2', location is LC4_A5, type is buried.
-- synthesized logic cell
_LC4_A5 = LCELL( _EQ010);
_EQ010 = FIVE2 & SS~2
# FOUR2 & SS~3;
-- Node name is '~126~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~126~3', location is LC5_A5, type is buried.
-- synthesized logic cell
_LC5_A5 = LCELL( _EQ011);
_EQ011 = ONE2 & !SS~6
# SIX2 & SS~1;
-- Node name is ':126' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ012);
_EQ012 = _LC6_A10
# _LC4_A5
# _LC5_A5;
-- Node name is '~128~1' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~128~1', location is LC3_A10, type is buried.
-- synthesized logic cell
_LC3_A10 = LCELL( _EQ013);
_EQ013 = SS~4 & THREE3
# SS~5 & TWO3;
-- Node name is '~128~2' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~128~2', location is LC7_A5, type is buried.
-- synthesized logic cell
_LC7_A5 = LCELL( _EQ014);
_EQ014 = FIVE3 & SS~2
# FOUR3 & SS~3;
-- Node name is '~128~3' from file "mulx6.tdf" line 32, column 11
-- Equation name is '~128~3', location is LC8_A5, type is buried.
-- synthesized logic cell
_LC8_A5 = LCELL( _EQ015);
_EQ015 = ONE3 & !SS~6
# SIX3 & SS~1;
-- Node name is ':128' from file "mulx6.tdf" line 32, column 11
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ016);
_EQ016 = _LC3_A10
# _LC7_A5
# _LC8_A5;
Project Information d:\zhuhui\mycpu\xianshi\mulx6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,246K
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?