p1ceshi.rpt
来自「vhd语言」· RPT 代码 · 共 547 行 · 第 1/2 页
RPT
547 行
- 5 - A 13 DFFE + 1 0 1 0 |7474:7|1Q (|7474:7|:9)
- 4 - A 17 DFFE + 1 0 1 0 |7474:7|2Q (|7474:7|:10)
- 1 - B 13 DFFE + 1 1 1 0 |7474:8|1Q (|7474:8|:9)
- 6 - B 16 DFFE + 1 1 1 0 |7474:8|2Q (|7474:8|:10)
- 3 - B 23 DFFE + 1 1 1 0 |7474:9|1Q (|7474:9|:9)
- 7 - C 23 DFFE + ! 1 1 1 0 |7474:9|2Q (|7474:9|:10)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\winnt\system32\nes\lx1111\p1ceshi.rpt
p1ceshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 2/ 48( 4%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 5/ 48( 10%) 5/16( 31%) 3/16( 18%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\winnt\system32\nes\lx1111\p1ceshi.rpt
p1ceshi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 T2
Device-Specific Information: c:\winnt\system32\nes\lx1111\p1ceshi.rpt
p1ceshi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 CLR
LCELL 1 :13
Device-Specific Information: c:\winnt\system32\nes\lx1111\p1ceshi.rpt
p1ceshi
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
CLR : INPUT;
P1 : INPUT;
R4 : INPUT;
R5 : INPUT;
R6 : INPUT;
R7 : INPUT;
T2 : INPUT;
T4 : INPUT;
-- Node name is 'PIN_NAME0'
-- Equation name is 'PIN_NAME0', type is output
PIN_NAME0 = _LC7_C23;
-- Node name is 'PIN_NAME1'
-- Equation name is 'PIN_NAME1', type is output
PIN_NAME1 = _LC3_B23;
-- Node name is 'PIN_NAME2'
-- Equation name is 'PIN_NAME2', type is output
PIN_NAME2 = _LC6_B16;
-- Node name is 'PIN_NAME3'
-- Equation name is 'PIN_NAME3', type is output
PIN_NAME3 = _LC1_B13;
-- Node name is 'PIN_NAME4'
-- Equation name is 'PIN_NAME4', type is output
PIN_NAME4 = _LC4_A17;
-- Node name is 'PIN_NAME5'
-- Equation name is 'PIN_NAME5', type is output
PIN_NAME5 = _LC5_A13;
-- Node name is '|7474:7|:9' = '|7474:7|1Q'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = DFFE( A5, GLOBAL( T2), GLOBAL( CLR), VCC, VCC);
-- Node name is '|7474:7|:10' = '|7474:7|2Q'
-- Equation name is '_LC4_A17', type is buried
_LC4_A17 = DFFE( A4, GLOBAL( T2), GLOBAL( CLR), VCC, VCC);
-- Node name is '|7474:8|:9' = '|7474:8|1Q'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE( A3, GLOBAL( T2), GLOBAL( CLR), _LC2_B16, VCC);
-- Node name is '|7474:8|:10' = '|7474:8|2Q'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = DFFE( A2, GLOBAL( T2), GLOBAL( CLR), _LC4_B16, VCC);
-- Node name is '|7474:9|:9' = '|7474:9|1Q'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = DFFE( A1, GLOBAL( T2), GLOBAL( CLR), _LC3_B16, VCC);
-- Node name is '|7474:9|:10' = '|7474:9|2Q'
-- Equation name is '_LC7_C23', type is buried
!_LC7_C23 = _LC7_C23~NOT;
_LC7_C23~NOT = DFFE(!A0, GLOBAL( T2), _LC1_B16, VCC, VCC);
-- Node name is ':10'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ001);
_EQ001 = !T4
# !P1
# !R7;
-- Node name is ':11'
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ002);
_EQ002 = !T4
# !P1
# !R6;
-- Node name is ':12'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = LCELL( _EQ003);
_EQ003 = !T4
# !P1
# !R5;
-- Node name is ':13'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ004);
_EQ004 = !R4
# !T4
# !P1;
Project Information c:\winnt\system32\nes\lx1111\p1ceshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,104K
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