h_adder1.vhd

来自「四位全加器」· VHDL 代码 · 共 13 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder1 IS
   port(a,b: IN STD_LOGIC;
			co,so:out STD_LOGIC);

END ENTITY h_adder1;
ARCHITECTURE fh1 OF h_adder1 IS
begin
   so<=NOT(a XOR(NOT b));
	co<=a AND b;
END ARCHITECTURE fh1;