or2a.vhd

四位全加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2a IS
   port(a,b: IN STD_LOGIC;
          c: OUT STD_LOGIC);

END ENTITY or2a;
ARCHITECTURE one OF or2a IS
    begin
	c<=a OR b;
      END ARCHITECTURE one;