sdr_top.tlg

使用FPGA做SDRAM控制器

Selecting top level module sdr_top
Synthesizing module sdr_ctrl
@N: CL201 :"E:\zhangmai\WORK\ip_porting\sdram_controller_xp\source\sdr_ctrl.v":160:0:160:5|Trying to extract state machine for register cState
Extracted state machine for register cState
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   1000
   1001
   1010
   1011
@N: CL201 :"E:\zhangmai\WORK\ip_porting\sdram_controller_xp\source\sdr_ctrl.v":116:0:116:5|Trying to extract state machine for register iState
Extracted state machine for register iState
State machine has 10 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
Synthesizing module sdr_sig
Synthesizing module sdr_data
Synthesizing module sdr_top