sdr_top.tcl

使用FPGA做SDRAM控制器

# ==== tcl script for synthesizing SDRAM Controller TOP on LATTICE-XP ==== #


# ======= Please change the following parameters as your env.
regexp -nocase {(.+)\/synthesis} [pwd] match home_dir
set device_name xm
set tech LATTICE-XP
set part LFXP10E
set speed {-5}
set package F388C
set proj_name sdr_top
#set design_type top
# ======= End



set source_dir $home_dir/source
set synmodel_dir $home_dir/models/$device_name/syn
set proj_dir $home_dir/synthesis/$device_name/synplicity

# Clean up old implementation
project -close eval("project -list")

# create a new project
project -new $proj_dir/$proj_name.prj

# Implementation version set
impl -remove [impl -list]

impl -add rev_1

add_file -verilog $source_dir/sdr_ctrl.v
add_file -verilog $source_dir/sdr_sig.v
add_file -verilog $source_dir/sdr_data.v
add_file -verilog $source_dir/sdr_top.v
impl -active "rev_1"

set_option -technology       $tech
set_option -part             $part
set_option -speed_grade      $speed
set_option -package          $package
set_option -resource_sharing 1
set_option -autosm           1
set_option -frequency        80.0000
set_option -top_module       sdr_top
set_option -_effort          high
set_option -fanout_limit     100
set_option -disable_io_insertion 0
set_option -force_gsr        auto

set_option -result_file       $proj_dir/rev_1/$proj_name.edn
project -run compile

project -run synthesis
save_project $proj_dir/$proj_name.prj