sdr_fsim.tcl

使用FPGA做SDRAM控制器

cd ../rtl

if {![file exists work]} {
     vlib work
}

vmap work work

# compile all necessary source and testbench files
#

# Start compiling.............
vlog +incdir+../../../../source ../../../../source/sdr_ctrl.v
vlog +incdir+../../../../source ../../../../source/sdr_sig.v
vlog +incdir+../../../../source ../../../../source/sdr_data.v
vlog +incdir+../../../../source ../../../../source/sdr_top.v

vlog +incdir+../../../../source ../../../../testbench/sdr_tb.tf

# End


# Load the top testbench file
vsim work.sdr_tb

add wave -r /*

run -all