config_space.vhd

来自「VHDL实现的奇偶校验功能模块和一个外设配置寄存器的设计实例。」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity config_space is
	port(
		rst,clk,wr:in std_logic;
		addr:in std_logic_vector(3 downto 0);
		data_in:in std_logic_vector(31 downto 0);
		data_out:out std_logic_vector(31 downto 0)
		);
end config_space;

architecture behave of config_space is
	type config_reg_type is array(15 downto 0) of std_logic_vector(31 downto 0);
	signal config_reg:config_reg_type;
	
	begin
		config_reg(0)<=x"11111172";
		config_reg(1)(15 downto 0)<=x"1234";
		
		process(clk)
			begin
				if rising_edge(clk) then
					if wr='1' then
						case addr is
						when x"1"=>
							config_reg(1)(31 downto 16)<=data_in(31 downto 16);
						when x"2"=>
							config_reg(2)(31 downto 0)<=data_in(31 downto 0);
						when others=>
							null;
						end case;
					else
						data_out(31 downto 0)<=config_reg(conv_integer(addr))(31 downto 0);
					end if;
				end if;
			end process;
end behave;