automake.log

UART 串口程序

ispLEVER Auto-Make Log File
---------------------------

Updating: JEDEC Report
Start to record tcl script...
Finished recording TCL script.

Starting: 'D:\program\isplever\ispfpga\bin\nt\edif2ngd.exe  -l mg5g00 -d LFXP3C "uart.edi" "uart.ngo"'

edif2ngd:  version ispLever_v61_PROD_Build (37)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights
     reserved.
Writing the design to uart.ngo...
Done: completed successfully.

Starting: 'D:\program\isplever\ispfpga\bin\nt\edfupdate.exe   -t "uart_v.tcy" -w "uart.ngo" -m "uart.ngo" "uart_v.ngx"'

edfupdate:  version ispLever_v61_PROD_Build (37)
Copyright (c) 2005 Lattice Semiconductor Corporation,  All rights reserved.

edfupdate finished successfully.

Done: completed successfully.

Starting: 'D:\program\isplever\ispfpga\bin\nt\ngdbuild.exe  -a mg5g00 -d LFXP3C -p "D:\program\isplever\ispfpga/mg5g00/data" "uart.ngo" "uart_v.ngd"'

ngdbuild:  version ispLever_v61_PROD_Build (37)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights
     reserved.
Reading 'uart.ngo' ...
Loading NGL library
     'D:/program/isplever/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library
     'D:/program/isplever/ispfpga/or5g00/data/orc5glib.ngl'...

Running DRC...
WARNING - ngdbuild: logical net 'u2/GNDZ1' has no driver
WARNING - ngdbuild: logical net 'u2/GNDZ1' has no load
WARNING - ngdbuild: logical net 'u2/VCCZ1' has no driver
WARNING - ngdbuild: logical net 'u2/VCCZ1' has no load
WARNING - ngdbuild: logical net 'u1/GNDZ1' has no driver
WARNING - ngdbuild: logical net 'u1/GNDZ1' has no load
WARNING - ngdbuild: logical net 'u1/VCCZ1' has no driver
WARNING - ngdbuild: logical net 'u1/VCCZ1' has no load
WARNING - ngdbuild: logical net 'GNDZ1' has no driver
WARNING - ngdbuild: logical net 'GNDZ1' has no load
WARNING - ngdbuild: logical net 'VCCZ1' has no driver
WARNING - ngdbuild: logical net 'VCCZ1' has no load
WARNING - ngdbuild: DRC complete with 12 warnings

Design Results:
    167 blocks expanded
complete the first expansion
Writing 'uart_v.ngd' ...

Done: completed successfully.

Starting: 'D:\program\isplever\ispfpga\bin\nt\map.exe  -a mg5g00 -p LFXP3C -t TQFP100 -s 3 "uart_v.ngd" -o "uart_v_map.ncd" -mp "uart_v.mrp" "uart_v.lpf"'

map:  version ispLever_v61_PROD_Build (37)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights
     reserved.
   Process the file: uart_v.ngd
   Picdevice="LFXP3C"
   Pictype="TQFP100"
   Picspeed=3
   Remove unused logic
   Do not produce over sized NCDs.
Part used: LFXP3CTQFP100, Speed used: 3.
Loading device for application map from file 'mg5g19x26.nph' in environment
     D:/program/isplever/ispfpga.
Package: Version 1.40, Status: FINAL
Running general design DRC...
WARNING - map: logical net 'u2/GNDZ1' has no driver
WARNING - map: logical net 'u2/VCCZ1' has no driver
WARNING - map: logical net 'u1/GNDZ1' has no driver
WARNING - map: logical net 'u1/VCCZ1' has no driver
WARNING - map: logical net 'GNDZ1' has no driver
WARNING - map: logical net 'VCCZ1' has no driver
Removing unused logic...
Optimizing...



Design Summary:
   Number of registers:    68
      PFU registers:    47
      PIO registers:    21
   Number of SLICEs:            43 out of  1536 (3%)
      SLICEs(logic/ROM):        43 out of  1152 (4%)
      SLICEs(logic/ROM/RAM):     0 out of   384 (0%)
          As RAM:            0
          As Logic/ROM:      0
   Number of logic LUT4s:      65
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:      0 (0 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:      65
   Number of external PIOs: 27 out of 62 (44%)
   Number of PIO IDDR/ODDR:     0
   Number of PIO FIXEDDELAY:    0
   Number of 3-state buffers:   0
   Number of PLLs:  0 out of 2 (0%)
   Number of block RAMs:  0 out of 6 (0%)
   Number of GSRs:  1 out of 1 (100%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
   Number of clocks:  4
     Net u1_clkdiv_3: 17 loads, 17 rising, 0 falling (Driver: u1/clkdivZ0Z_3 )
     Net clk16x_c: 12 loads, 12 rising, 0 falling (Driver: PIO clk16x )
     Net wrn_c: 8 loads, 8 rising, 0 falling (Driver: PIO wrn )
     Net u2/clkdivZ0Z_3: 14 loads, 8 rising, 6 falling (Driver: u2/clkdiv_3 )
   Number of Clock Enables:  10
     Net un1_parity7_2: 1 loads, 0 LSLICEs
     Net u2_N_23_i: 1 loads, 0 LSLICEs
     Net u2/un1_clk1x_enableZ0Z11: 1 loads, 1 LSLICEs
     Net u2/N_24_iZ0: 5 loads, 5 LSLICEs
     Net u2_parity9: 1 loads, 1 LSLICEs
     Net u2_N_26_i: 1 loads, 0 LSLICEs
     Net u2_un1_clk1x_enable10_2_i: 1 loads, 0 LSLICEs
     Net u1_parity7: 5 loads, 5 LSLICEs
     Net u1/N_29_iZ0: 1 loads, 1 LSLICEs
     Net u1_parity8: 8 loads, 0 LSLICEs
   Number of LSRs:  3
     Net u2/N_27_iZ0: 6 loads, 6 LSLICEs
     Net u1/N_30_iZ0: 1 loads, 1 LSLICEs
     Net u1/N_31_iZ0: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net u2_no_bits_sent_0: 12 loads
     Net u2_no_bits_sent_1: 11 loads
     Net u1_parity8: 10 loads
     Net rdn_c: 9 loads
     Net u1_no_bits_rcvd_0: 8 loads
     Net u1_no_bits_rcvd_1: 8 loads
     Net u2/parityZ0Z7: 8 loads
     Net u2_no_bits_sent_2: 8 loads
     Net u1_parity7: 7 loads
     Net u2_no_bits_sent_3: 7 loads

Total CPU Time: 0 secs  
Total REAL Time: 2 secs  
Peak Memory Usage: 25 MB

Dumping design to file uart_v_map.ncd.

Done: completed successfully.

Starting: 'D:\program\isplever\ispcpld\bin\checkpoint.exe -m -f "uart_v.cmm" -f "uart_v.cm2" -arch mg5g00 "uart_v_map.ncd"'


---- Checkpoint Tool Log File ----
Logic percent not specified. Using 60 logic percent for architecture mg5g00.

==== Trace Standard Out ====
trce:  version ispLever_v61_PROD_Build (37)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights
     reserved.

Loading design for application trce from file uart_v_map.ncd.
Design name: uart
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP3C
Package:     TQFP100
Speed:       3
Loading device for application trce from file 'mg5g19x26.nph' in
environment D:/program/isplever/ispfpga.
Package: Version 1.40, Status: FINAL
Speed Hardware Data: version 9.999
--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v61_PROD_Build (37)
Tue Jul 17 10:48:29 2007

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -o checkpnt.twr uart_v_map.ncd uart_v.prf 
Design file:     uart_v_map.ncd
Preference file: uart_v.prf
Device,speed:    LFXP3C,3
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



Timing summary:
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 314 paths, 5 nets, and 321 connections (86.5% coverage)

--------------------------------------------------------------------------------

Total time: 2 secs 
==== End of Trace Standard Out ====

*********************************
Map checkpoint failed.
Design's logic delay (69 percent of total delay) 
exceeds the 60 percent limit set in the map checkpoint options
*********************************
 Process Continuing ...

Done: completed successfully.

Starting: 'D:\program\isplever\ispcpld\bin\multipar.exe -p uart_v.p2t -f "uart_v.p3t" "uart_v_map.ncd" "uart_v.ncd"'


Removing old design directory at request of -rem command line option to
this program.
Running par. Please wait . . .

Lattice Place and Route Report for Design "uart_v_map.ncd"
Tue Jul 17 10:48:30 2007

PAR: Place And Route ispLever_v61_PROD_Build (37).
Command line: D:/program/isplever/ispfpga\bin\nt\par -f uart_v.p2t uart_v_map.ncd uart_v.dir
uart_v.prf
Preference file: uart_v.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file uart_v_map.ncd.
Design name: uart
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP3C
Package:     TQFP100