📄 uart_v.tw1
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Lattice TRACE Report, Version ispLever_v61_PROD_Build (37)
Tue Jul 17 10:48:29 2007
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -o checkpnt.twr uart_v_map.ncd uart_v.prf
Design file: uart_v_map.ncd
Preference file: uart_v.prf
Device,speed: LFXP3C,3
Report level: verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "clk16x" 177.054000 MHz ;
0 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 3.729ns
The internal maximum frequency of the following component is 521.376 MHz
Logical Details: Cell type Pin type Component name
Source: FSLICE Clock u2/SLICE_17
Destination: FSLICE Data in u2/SLICE_17
Delay: 1.918ns -- based on Minimum Pulse Width
Report: 521.376MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "u1_clkdiv_3" 360.750000 MHz ;
105 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.854ns
The internal maximum frequency of the following component is 521.376 MHz
Logical Details: Cell type Pin type Component name
Source: FSLICE Clock u1/SLICE_1
Destination: FSLICE Data in u1/SLICE_1
Delay: 1.918ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 1.164ns
and meets 5.647ns delay constraint requirement for source clock "clk16x_c" by 4.039ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u1/clk1x_enable (from clk16x_c +)
Destination: FF Unknown u1/no_bits_rcvdZ0Z_1 (to u1_clkdiv_3 +)
FF u1/no_bits_rcvdZ0Z_0
Delay: 0.958ns (100.0% logic, 0.0% route), 2 logic levels.
Constraint Details:
0.958ns physical path delay u1/SLICE_2 to u1/SLICE_8 meets
2.772ns delay constraint less
0.650ns LSRREC_SET requirement (totaling 2.122ns) by 1.164ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.576 u1/SLICE_2.CLK to u1/SLICE_2.Q0 u1/SLICE_2 (from clk16x_c)
ROUTE 5 e 0.000 u1/SLICE_2.Q0 to u1/SLICE_42.B0 u1/clk1x_enableZ0
CTOF_DEL --- 0.382 u1/SLICE_42.B0 to u1/SLICE_42.F0 u1/SLICE_42
ROUTE 2 e 0.000 u1/SLICE_42.F0 to u1/SLICE_8.LSR u1/N_31_iZ0 (to u1_clkdiv_3)
--------
0.958 (100.0% logic, 0.0% route), 2 logic levels.
Report: 521.376MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clk16x_c" 364.564000 MHz ;
61 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.825ns
The internal maximum frequency of the following component is 521.376 MHz
Logical Details: Cell type Pin type Component name
Source: FSLICE Clock u1/SLICE_0
Destination: FSLICE Data in u1/SLICE_0
Delay: 1.918ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 1.152ns
and meets 5.647ns delay constraint requirement for source clock "u1_clkdiv_3" by 4.056ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u1/no_bits_rcvdZ0Z_1 (from u1_clkdiv_3 +)
Destination: FF Unknown u1/clk1x_enable (to clk16x_c +)
Delay: 1.340ns (100.0% logic, 0.0% route), 3 logic levels.
Constraint Details:
1.340ns physical path delay u1/SLICE_8 to u1/SLICE_2 meets
2.743ns delay constraint less
0.251ns CE_SET requirement (totaling 2.492ns) by 1.152ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.576 u1/SLICE_8.CLK to u1/SLICE_8.Q1 u1/SLICE_8 (from u1_clkdiv_3)
ROUTE 8 e 0.000 u1/SLICE_8.Q1 to u1/SLICE_33.A0 u1_no_bits_rcvd_1
CTOF_DEL --- 0.382 u1/SLICE_33.A0 to u1/SLICE_33.F0 u1/SLICE_33
ROUTE 1 e 0.000 u1/SLICE_33.F0 to u1/SLICE_33.D1 u1/un1_no_bits_rcvd_1Z0Z_0
CTOF_DEL --- 0.382 u1/SLICE_33.D1 to u1/SLICE_33.F1 u1/SLICE_33
ROUTE 1 e 0.000 u1/SLICE_33.F1 to u1/SLICE_2.CE u1/N_29_iZ0 (to clk16x_c)
--------
1.340 (100.0% logic, 0.0% route), 3 logic levels.
Report: 521.376MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "u2/clkdivZ0Z_3" 177.054000 MHz ;
148 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1.185ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u2/no_bits_sent_0_repZ0Z1 (from u2/clkdivZ0Z_3 +)
Destination: FF Unknown u2_sdoio (to u2/clkdivZ0Z_3 -)
Delay: 1.722ns (100.0% logic, 0.0% route), 4 logic levels.
Constraint Details:
1.722ns physical path delay SLICE_24 to sdo_MGIOL meets
2.823ns delay constraint less
-0.084ns ONEG0_SET requirement (totaling 2.907ns) by 1.185ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.576 SLICE_24.CLK to SLICE_24.Q0 SLICE_24 (from u2/clkdivZ0Z_3)
ROUTE 6 e 0.000 SLICE_24.Q0 to SLICE_31.B1 u2_no_bits_sent_0_rep1
CTOF_DEL --- 0.382 SLICE_31.B1 to SLICE_31.F1 SLICE_31
ROUTE 1 e 0.000 SLICE_31.F1 to SLICE_31.A0 g0_7_xZ0Z0
CTOF_DEL --- 0.382 SLICE_31.A0 to SLICE_31.F0 SLICE_31
ROUTE 1 e 0.000 SLICE_31.F0 to SLICE_36.A1 g0Z0Z_7
CTOF_DEL --- 0.382 SLICE_36.A1 to SLICE_36.F1 SLICE_36
ROUTE 1 e 0.000 SLICE_36.F1 to do_MGIOL.ONEG0 u2_N_22_i (to u2/clkdivZ0Z_3)
--------
1.722 (100.0% logic, 0.0% route), 4 logic levels.
Report: 305.250MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "clk16x" 177.054000 MHz | | |
; | 177.054 MHz| 521.376 MHz| 0
| | |
FREQUENCY NET "u1_clkdiv_3" 360.750000 | | |
MHz ; | 360.750 MHz| 521.376 MHz| 2
| | |
FREQUENCY NET "clk16x_c" 364.564000 MHz | | |
; | 364.564 MHz| 521.376 MHz| 3
| | |
FREQUENCY NET "u2/clkdivZ0Z_3" | | |
177.054000 MHz ; | 177.054 MHz| 305.250 MHz| 4
| | |
----------------------------------------------------------------------------
All preferences were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 314 paths, 5 nets, and 321 connections (86.5% coverage)
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