uart.tlg

UART 串口程序

Selecting top level module uart
@N: CG364 :"F:\CUSTMO~1\uart_verilog\rcvr.v":23:7:23:10|Synthesizing module rcvr

@N: CG364 :"F:\CUSTMO~1\uart_verilog\txmit.v":23:7:23:11|Synthesizing module txmit

@N: CG364 :"F:\CUSTMO~1\uart_verilog\uart.v":24:7:24:10|Synthesizing module uart