uart.vm

UART 串口程序

// @4:83
  IFS1P3DX \u2_tbrio_Z[3]  (
	.D(din_c[3]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [3])
);
// @4:83
  IFS1P3DX \u2_tbrio_Z[4]  (
	.D(din_c[4]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [4])
);
// @4:83
  IFS1P3DX \u2_tbrio_Z[5]  (
	.D(din_c[5]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [5])
);
// @4:83
  IFS1P3DX \u2_tbrio_Z[6]  (
	.D(din_c[6]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [6])
);
// @4:83
  IFS1P3DX \u2_tbrio_Z[7]  (
	.D(din_c[7]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [7])
);
// @5:52
  IFS1P3BX u1_rxd1io_Z (
	.D(rxd_c),
	.SP(VCC),
	.SCLK(clk16x_c),
	.PD(GND),
	.Q(\u1.rxd1 )
);
// @4:101
  OFS1P3BX u2_tsreio_Z (
	.D(\u2.no_bits_sent [2]),
	.SP(\u2.N_26_i ),
	.SCLK(\u2.clkdiv_i_0 [3]),
	.PD(GND),
	.Q(tsre_c)
);
// @4:62
  OFS1P3DX u2_tbreio_Z (
	.D(\u2.N_21_i ),
	.SP(\u2.un1_clk1x_enable10_2_i ),
	.SCLK(clk16x_c),
	.CD(GND),
	.Q(tbre_c)
);
// @4:101
  OFS1P3BX u2_sdoio_Z (
	.D(\u2.N_22_i ),
	.SP(\u2.N_23_i ),
	.SCLK(\u2.clkdiv_i_0 [3]),
	.PD(GND),
	.Q(sdo_c)
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[0]  (
	.D(\u1.rsr [0]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [0])
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[1]  (
	.D(\u1.rsr [1]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [1])
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[2]  (
	.D(\u1.rsr [2]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [2])
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[3]  (
	.D(\u1.rsr [3]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [3])
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[4]  (
	.D(\u1.rsr [4]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [4])
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[5]  (
	.D(\u1.rsr [5]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [5])
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[6]  (
	.D(\u1.rsr [6]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [6])
);
// @5:97
  OFS1P3DX \u1_rbrio_Z[7]  (
	.D(\u1.rsr [7]),
	.SP(\u1.parity8 ),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(\u1.rbr [7])
);
// @5:97
  OFS1P3DX u1_framing_errorio_Z (
	.D(N_25_a2),
	.SP(un1_parity7_2),
	.SCLK(\u1.clkdiv [3]),
	.CD(GND),
	.Q(framing_error_c)
);
  GSR GSR_INST (
	.GSR(GSRN)
);
  INV GSRN_cZ (
	.A(rst_c),
	.Z(GSRN)
);
// @6:28
  OB sdo_pad (
	.I(sdo_c),
	.O(sdo)
);
// @6:32
  IB wrn_pad (
	.I(wrn),
	.O(wrn_c)
);
// @6:27
  OB tsre_pad (
	.I(tsre_c),
	.O(tsre)
);
// @6:26
  OB tbre_pad (
	.I(tbre_c),
	.O(tbre)
);
// @6:29
  IB \din_pad[7]  (
	.I(din[7]),
	.O(din_c[7])
);
// @6:29
  IB \din_pad[6]  (
	.I(din[6]),
	.O(din_c[6])
);
// @6:29
  IB \din_pad[5]  (
	.I(din[5]),
	.O(din_c[5])
);
// @6:29
  IB \din_pad[4]  (
	.I(din[4]),
	.O(din_c[4])
);
// @6:29
  IB \din_pad[3]  (
	.I(din[3]),
	.O(din_c[3])
);
// @6:29
  IB \din_pad[2]  (
	.I(din[2]),
	.O(din_c[2])
);
// @6:29
  IB \din_pad[1]  (
	.I(din[1]),
	.O(din_c[1])
);
// @6:29
  IB \din_pad[0]  (
	.I(din[0]),
	.O(din_c[0])
);
// @6:34
  IB rdn_pad (
	.I(rdn),
	.O(rdn_c)
);
// @6:30
  IB rst_pad (
	.I(rst),
	.O(rst_c)
);
// @6:31
  IB clk16x_pad (
	.I(clk16x),
	.O(clk16x_c)
);
// @6:33
  IB rxd_pad (
	.I(rxd),
	.O(rxd_c)
);
// @6:38
  OB parity_error_pad (
	.I(parity_error_c),
	.O(parity_error)
);
// @6:37
  OB framing_error_pad (
	.I(framing_error_c),
	.O(framing_error)
);
// @6:36
  OB data_ready_pad (
	.I(data_ready_c),
	.O(data_ready)
);
// @6:35
  OBZ \dout_pad[7]  (
	.I(\u1.rbr [7]),
	.T(rdn_c),
	.O(dout[7])
);
// @6:35
  OBZ \dout_pad[6]  (
	.I(\u1.rbr [6]),
	.T(rdn_c),
	.O(dout[6])
);
// @6:35
  OBZ \dout_pad[5]  (
	.I(\u1.rbr [5]),
	.T(rdn_c),
	.O(dout[5])
);
// @6:35
  OBZ \dout_pad[4]  (
	.I(\u1.rbr [4]),
	.T(rdn_c),
	.O(dout[4])
);
// @6:35
  OBZ \dout_pad[3]  (
	.I(\u1.rbr [3]),
	.T(rdn_c),
	.O(dout[3])
);
// @6:35
  OBZ \dout_pad[2]  (
	.I(\u1.rbr [2]),
	.T(rdn_c),
	.O(dout[2])
);
// @6:35
  OBZ \dout_pad[1]  (
	.I(\u1.rbr [1]),
	.T(rdn_c),
	.O(dout[1])
);
// @6:35
  OBZ \dout_pad[0]  (
	.I(\u1.rbr [0]),
	.T(rdn_c),
	.O(dout[0])
);
assign \u2.un1_no_bits_sent_3_p4  = (~\u2.no_bits_sent_fast [0] & ~\u2.no_bits_sent_fast [2] & 
   ~\u2.no_bits_sent_fast [3]) | (~\u2.no_bits_sent_fast [1] & ~\u2.no_bits_sent_fast [2] & 
   ~\u2.no_bits_sent_fast [3]) | (~\u2.no_bits_sent_fast [0] & \u2.no_bits_sent_fast [1] & 
   ~\u2.no_bits_sent_fast [2] & ~\u2.no_bits_sent_fast [3]);
assign g0_2 = (~\u2.no_bits_sent [1]) | (~\u2.no_bits_sent [1] & ~\u2.no_bits_sent [2]) | 
   (\u2.no_bits_sent [2]) | (\u2.no_bits_sent [0] & ~\u2.no_bits_sent [3]) | 
   (~\u2.no_bits_sent [1] & ~\u2.no_bits_sent [3]) | (\u2.no_bits_sent [0] & 
   \u2.no_bits_sent [1] & ~\u2.no_bits_sent [3]) | (\u2.no_bits_sent [0] & 
   ~\u2.no_bits_sent [2] & ~\u2.no_bits_sent [3]) | (~\u2.no_bits_sent [1] & 
   ~\u2.no_bits_sent [2] & ~\u2.no_bits_sent [3]) | (\u2.no_bits_sent [0] & 
   \u2.no_bits_sent [1] & ~\u2.no_bits_sent [2] & ~\u2.no_bits_sent [3]) | 
   (\u2.no_bits_sent [2] & ~\u2.no_bits_sent [3]) | (~\u2.no_bits_sent [0] & 
   \u2.no_bits_sent [3]) | (~\u2.no_bits_sent [1] & \u2.no_bits_sent [3]) | 
   (~\u2.no_bits_sent [0] & \u2.no_bits_sent [1] & \u2.no_bits_sent [3]) | 
   (~\u2.no_bits_sent [0] & ~\u2.no_bits_sent [2] & \u2.no_bits_sent [3]) | 
   (~\u2.no_bits_sent [1] & ~\u2.no_bits_sent [2] & \u2.no_bits_sent [3]) | 
   (~\u2.no_bits_sent [0] & \u2.no_bits_sent [1] & ~\u2.no_bits_sent [2] & 
   \u2.no_bits_sent [3]) | (\u2.no_bits_sent [2] & \u2.no_bits_sent [3]);
assign \u2.un3_p4  = (\u2.no_bits_sent_2_rep1  & \u2.no_bits_sent_fast [3]) | 
   (\u2.no_bits_sent_2_rep1  & ~\u2.no_bits_sent_fast [1] & \u2.no_bits_sent_fast [3]) | 
   (\u2.no_bits_sent_0_rep1  & \u2.no_bits_sent_fast [1] & \u2.no_bits_sent_fast [3]) | 
   (\u2.no_bits_sent_0_rep1  & ~\u2.no_bits_sent_2_rep1  & \u2.no_bits_sent_fast [1] & 
   \u2.no_bits_sent_fast [3]) | (\u2.no_bits_sent_2_rep1  & \u2.no_bits_sent_fast [1] & 
   \u2.no_bits_sent_fast [3]);
assign \u2.N_23_i  = (~g0_2) | (~g0_2 & ~\u2.parity11 ) | (\u2.parity11 ) | 
   (~g0_2 & ~\u2.un3_p4 ) | (~g0_2 & ~\u2.parity11  & ~\u2.un3_p4 ) | (\u2.parity11  & 
   ~\u2.un3_p4 ) | (~\u2.un1_no_bits_sent_3_p4  & ~\u2.un3_p4 ) | (~g0_2 & 
   \u2.un1_no_bits_sent_3_p4  & ~\u2.un3_p4 ) | (~g0_2 & ~\u2.parity11  & 
   \u2.un1_no_bits_sent_3_p4  & ~\u2.un3_p4 ) | (\u2.parity11  & \u2.un1_no_bits_sent_3_p4  & 
   ~\u2.un3_p4 ) | (~g0_2 & \u2.un3_p4 ) | (~g0_2 & ~\u2.parity11  & \u2.un3_p4 ) | 
   (\u2.parity11  & \u2.un3_p4 );
assign \u2.parity11  = (\u2.no_bits_sent [3] & ~\u2.no_bits_sent_0_rep1  & 
   \u2.no_bits_sent_2_rep1  & ~\u2.no_bits_sent_fast [1]);
assign \u2.parity9  = (\u2.no_bits_sent [1] & ~\u2.no_bits_sent [3] & \u2.no_bits_sent_0_rep1 ) | 
   (~\u2.no_bits_sent [1] & \u2.no_bits_sent [3] & ~\u2.no_bits_sent_2_rep1 ) | 
   (\u2.no_bits_sent [3] & ~\u2.no_bits_sent_0_rep1  & ~\u2.no_bits_sent_2_rep1 ) | 
   (\u2.no_bits_sent [1] & ~\u2.no_bits_sent [3] & \u2.no_bits_sent_0_rep1  & 
   ~\u2.no_bits_sent_2_rep1 ) | (~\u2.no_bits_sent [1] & \u2.no_bits_sent [3] & 
   \u2.no_bits_sent_0_rep1  & ~\u2.no_bits_sent_2_rep1 ) | (~\u2.no_bits_sent [3] & 
   \u2.no_bits_sent_2_rep1 );
assign \u2.N_22_i  = (g0_7) | (g0_7 & ~\u2.parity11 ) | (\u2.parity11 ) | 
   (g0_7 & ~\u2.tsr [7]) | (g0_7 & ~\u2.parity11  & ~\u2.tsr [7]) | (\u2.parity11  & 
   ~\u2.tsr [7]) | (g0_7 & \u2.tsr [7]) | (g0_7 & ~\u2.parity9  & \u2.tsr [7]) | 
   (\u2.parity9  & \u2.tsr [7]) | (g0_7 & ~\u2.parity11  & \u2.tsr [7]) | 
   (g0_7 & ~\u2.parity9  & ~\u2.parity11  & \u2.tsr [7]) | (\u2.parity9  & 
   ~\u2.parity11  & \u2.tsr [7]) | (\u2.parity11  & \u2.tsr [7]);
assign \u1.parity7  = (\u1.no_bits_rcvd [0] & ~\u1.no_bits_rcvd [1] & ~\u1.no_bits_rcvd [2]) | 
   (\u1.no_bits_rcvd [0] & ~\u1.no_bits_rcvd [3]) | (\u1.no_bits_rcvd [0] & 
   ~\u1.no_bits_rcvd [1] & ~\u1.no_bits_rcvd [3]) | (\u1.no_bits_rcvd [1] & 
   ~\u1.no_bits_rcvd [3]) | (\u1.no_bits_rcvd [0] & ~\u1.no_bits_rcvd [2] & 
   ~\u1.no_bits_rcvd [3]) | (\u1.no_bits_rcvd [0] & ~\u1.no_bits_rcvd [1] & 
   ~\u1.no_bits_rcvd [2] & ~\u1.no_bits_rcvd [3]) | (\u1.no_bits_rcvd [1] & 
   ~\u1.no_bits_rcvd [2] & ~\u1.no_bits_rcvd [3]) | (\u1.no_bits_rcvd [2] & 
   ~\u1.no_bits_rcvd [3]) | (~\u1.no_bits_rcvd [1] & ~\u1.no_bits_rcvd [2] & 
   \u1.no_bits_rcvd [3]);
assign g0_7_x0 = (\u2.no_bits_sent [1] & \u2.no_bits_sent_0_rep1  & \u2.no_bits_sent_fast [3] & 
   \u2.parity );
assign g0_7 = (g0_7_x0 & ~\u2.no_bits_sent [2]);
// @6:40
  rcvr u1 (
	.rsr({\u1.rsr [7], \u1.rsr [6], \u1.rsr [5], \u1.rsr [4], \u1.rsr [3], \u1.rsr [2], 
   \u1.rsr [1], \u1.rsr [0]}),
	.clkdiv_3(\u1.clkdiv [3]),
	.no_bits_rcvd({\u1.no_bits_rcvd [3], \u1.no_bits_rcvd [2], \u1.no_bits_rcvd [1], 
   \u1.no_bits_rcvd [0]}),
	.un1_parity7_2(un1_parity7_2),
	.N_25_a2(N_25_a2),
	.rst_c(rst_c),
	.rdn_c(rdn_c),
	.VCC(VCC),
	.GSRN(GSRN),
	.clk16x_c(clk16x_c),
	.rxd1(\u1.rxd1 ),
	.GND(GND),
	.data_ready_c(data_ready_c),
	.parity7(\u1.parity7 ),
	.parity8(\u1.parity8 ),
	.parity_error_c(parity_error_c)
);
// @6:42
  txmit u2 (
	.tbr({\u2.tbr [7], \u2.tbr [6], \u2.tbr [5], \u2.tbr [4], \u2.tbr [3], \u2.tbr [2], 
   \u2.tbr [1], \u2.tbr [0]}),
	.tsr_7(\u2.tsr [7]),
	.no_bits_sent_fast({\u2.no_bits_sent_fast [3], \u2.no_bits_sent_fast [2], 
   \u2.no_bits_sent_fast [1], \u2.no_bits_sent_fast [0]}),
	.no_bits_sent({\u2.no_bits_sent [3], \u2.no_bits_sent [2], \u2.no_bits_sent [1], 
   \u2.no_bits_sent [0]}),
	.clkdiv_i_0(\u2.clkdiv_i_0 [3]),
	.un1_clk1x_enable10_2_i(\u2.un1_clk1x_enable10_2_i ),
	.N_26_i(\u2.N_26_i ),
	.rst_c(rst_c),
	.VCC(VCC),
	.parity(\u2.parity ),
	.parity9(\u2.parity9 ),
	.wrn_c(wrn_c),
	.GSRN(GSRN),
	.clk16x_c(clk16x_c),
	.N_21_i(\u2.N_21_i ),
	.GND(GND),
	.no_bits_sent_2_rep1(\u2.no_bits_sent_2_rep1 ),
	.no_bits_sent_0_rep1(\u2.no_bits_sent_0_rep1 )
);
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
endmodule /* uart */