uart.vm

UART 串口程序

   ~no_bits_sent[1] & no_bits_sent[0]) | (no_bits_sent_fast[3] & ~no_bits_sent[2] & 
   no_bits_sent[1] & no_bits_sent[0]) | (~no_bits_sent_fast[3] & no_bits_sent[2] & 
   no_bits_sent[1] & no_bits_sent[0]);
assign no_bits_sent_n2_rep1 = (no_bits_sent_2_rep1 & ~no_bits_sent[1]) | 
   (no_bits_sent_2_rep1 & ~no_bits_sent[0]) | (no_bits_sent_2_rep1 & ~no_bits_sent[1] & 
   no_bits_sent[0]) | (~no_bits_sent_2_rep1 & no_bits_sent[1] & no_bits_sent[0]);
assign no_bits_sent_n2_fast = (no_bits_sent_fast[2] & ~no_bits_sent[1]) | 
   (no_bits_sent_fast[2] & ~no_bits_sent[0]) | (no_bits_sent_fast[2] & 
   ~no_bits_sent[1] & no_bits_sent[0]) | (~no_bits_sent_fast[2] & no_bits_sent[1] & 
   no_bits_sent[0]);
assign un1_clk1x_enable11 = (~un1_clk1x_enable10_2_0 & no_bits_sent[0]) | 
   (~un1_clk1x_enable10_2_0 & no_bits_sent[0] & ~wrn1) | (~un1_clk1x_enable10_2_0 & 
   no_bits_sent[0] & ~wrn2 & ~wrn1) | (wrn2 & ~wrn1) | (~un1_clk1x_enable10_2_0 & 
   no_bits_sent[0] & wrn1);
assign no_bits_sent_n3 = (no_bits_sent[3] & ~no_bits_sent[2]) | (no_bits_sent[3] & 
   ~no_bits_sent[1]) | (no_bits_sent[3] & ~no_bits_sent[2] & no_bits_sent[1]) | 
   (no_bits_sent[3] & ~no_bits_sent[0]) | (no_bits_sent[3] & ~no_bits_sent[2] & 
   no_bits_sent[0]) | (no_bits_sent[3] & ~no_bits_sent[1] & no_bits_sent[0]) | 
   (no_bits_sent[3] & ~no_bits_sent[2] & no_bits_sent[1] & no_bits_sent[0]) | 
   (~no_bits_sent[3] & no_bits_sent[2] & no_bits_sent[1] & no_bits_sent[0]);
assign N_21_i = (~no_bits_sent[3]) | (~no_bits_sent[3] & ~wrn1) | (~no_bits_sent[3] & 
   ~wrn2 & ~wrn1) | (wrn2 & ~wrn1) | (~no_bits_sent[3] & wrn1);
assign no_bits_sent_n2 = (no_bits_sent[2] & ~no_bits_sent[1]) | (no_bits_sent[2] & 
   ~no_bits_sent[0]) | (no_bits_sent[2] & ~no_bits_sent[1] & no_bits_sent[0]) | 
   (~no_bits_sent[2] & no_bits_sent[1] & no_bits_sent[0]);
// @4:48
  FD1S3AY wrn2_Z (
	.D(wrn1),
	.CK(clk16x_c),
	.Q(wrn2)
);
// @4:48
  FD1S3AY wrn1_Z (
	.D(wrn_c),
	.CK(clk16x_c),
	.Q(wrn1)
);
// @4:101
  FD1P3AX \tsr_Z[0]  (
	.D(tsr_6[0]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr[0])
);
// @4:101
  FD1P3AX \tsr_Z[1]  (
	.D(tsr_6[1]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr[1])
);
// @4:101
  FD1P3AX \tsr_Z[2]  (
	.D(tsr_6[2]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr[2])
);
// @4:101
  FD1P3AX \tsr_Z[3]  (
	.D(tsr_6[3]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr[3])
);
// @4:101
  FD1P3AX \tsr_Z[4]  (
	.D(tsr_6[4]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr[4])
);
// @4:101
  FD1P3AX \tsr_Z[5]  (
	.D(tsr_6[5]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr[5])
);
// @4:101
  FD1P3AX \tsr_Z[6]  (
	.D(tsr_6[6]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr[6])
);
// @4:101
  FD1P3AX \tsr_Z[7]  (
	.D(tsr_6[7]),
	.SP(N_24_i),
	.CK(clkdiv_i_0[3]),
	.Q(tsr_7)
);
// @4:101
  FD1P3AY parity_Z (
	.D(parity_3),
	.SP(parity9),
	.CK(clkdiv_i_0[3]),
	.Q(parity)
);
// @4:140
  FD1S3DX \no_bits_sent_Z[0]  (
	.D(no_bits_sent_i[0]),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent[0])
);
defparam \no_bits_sent_Z[0] .GSR="DISABLED";
// @4:140
  FD1S3DX \no_bits_sent_fast_Z[0]  (
	.D(no_bits_sent_fast_i[0]),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent_fast[0])
);
defparam \no_bits_sent_fast_Z[0] .GSR="DISABLED";
// @4:140
  FD1S3DX \no_bits_sent_fast_Z[1]  (
	.D(no_bits_sent_n1_fast),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent_fast[1])
);
defparam \no_bits_sent_fast_Z[1] .GSR="DISABLED";
// @4:140
  FD1S3DX no_bits_sent_2_rep1_Z (
	.D(no_bits_sent_n2_rep1),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent_2_rep1)
);
defparam no_bits_sent_2_rep1_Z.GSR="DISABLED";
// @4:140
  FD1S3DX no_bits_sent_0_rep1_Z (
	.D(no_bits_sent_0_rep1_i),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent_0_rep1)
);
defparam no_bits_sent_0_rep1_Z.GSR="DISABLED";
// @4:140
  FD1S3DX \no_bits_sent_Z[1]  (
	.D(no_bits_sent_n1),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent[1])
);
defparam \no_bits_sent_Z[1] .GSR="DISABLED";
// @4:140
  FD1S3DX \no_bits_sent_fast_Z[2]  (
	.D(no_bits_sent_n2_fast),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent_fast[2])
);
defparam \no_bits_sent_fast_Z[2] .GSR="DISABLED";
// @4:140
  FD1S3DX \no_bits_sent_Z[2]  (
	.D(no_bits_sent_n2),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent[2])
);
defparam \no_bits_sent_Z[2] .GSR="DISABLED";
// @4:140
  FD1S3DX \no_bits_sent_fast_Z[3]  (
	.D(no_bits_sent_n3_fast),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent_fast[3])
);
defparam \no_bits_sent_fast_Z[3] .GSR="DISABLED";
// @4:140
  FD1S3DX \no_bits_sent_Z[3]  (
	.D(no_bits_sent_n3),
	.CK(clkdiv[3]),
	.CD(N_27_i),
	.Q(no_bits_sent[3])
);
defparam \no_bits_sent_Z[3] .GSR="DISABLED";
// @4:91
  FD1S3AX \clkdiv_Z[0]  (
	.D(clkdiv_4[0]),
	.CK(clk16x_c),
	.Q(clkdiv[0])
);
// @4:91
  FD1S3AX \clkdiv_Z[1]  (
	.D(clkdiv_4[1]),
	.CK(clk16x_c),
	.Q(clkdiv[1])
);
// @4:91
  FD1S3AX \clkdiv_Z[2]  (
	.D(clkdiv_4[2]),
	.CK(clk16x_c),
	.Q(clkdiv[2])
);
// @4:91
  FD1S3AX \clkdiv_Z[3]  (
	.D(clkdiv_4[3]),
	.CK(clk16x_c),
	.Q(clkdiv[3])
);
// @4:62
  FD1P3AX clk1x_enable_Z (
	.D(clk1x_enable10),
	.SP(un1_clk1x_enable11),
	.CK(clk16x_c),
	.Q(clk1x_enable)
);
assign clkdiv_4_p4 = (clk1x_enable & clkdiv[0] & clkdiv[1] & clkdiv[2]);
assign no_bits_sent_n1 = (no_bits_sent[0] & ~no_bits_sent[1]) | (~no_bits_sent[0] & 
   no_bits_sent[1]);
assign clk1x_enable10 = (~wrn1 & wrn2);
assign parity_3 = (parity & ~tsr_7) | (~parity & tsr_7);
assign clkdiv_4[0] = (clk1x_enable & ~clkdiv[0]) | (~clk1x_enable & clkdiv[0]);
assign clkdiv_4[3] = (clkdiv[3] & ~clkdiv_4_p4) | (~clkdiv[3] & clkdiv_4_p4);
assign N_27_i = (rst_c) | (~clk1x_enable) | (rst_c & clk1x_enable);
assign clkdiv_4[1] = (clk1x_enable & clkdiv[0] & ~clkdiv[1]) | (~clk1x_enable & 
   clkdiv[1]) | (~clkdiv[0] & clkdiv[1]) | (~clk1x_enable & clkdiv[0] & 
   clkdiv[1]);
assign parity7 = (no_bits_sent_fast[0] & ~no_bits_sent_fast[1] & ~no_bits_sent_fast[2] & 
   ~no_bits_sent_fast[3]);
assign tsr_6[0] = (parity7 & tbr[0]);
assign clkdiv_4[2] = (clk1x_enable & clkdiv[0] & clkdiv[1] & ~clkdiv[2]) | 
   (~clk1x_enable & clkdiv[2]) | (~clkdiv[0] & clkdiv[2]) | (~clk1x_enable & 
   clkdiv[0] & clkdiv[2]) | (~clkdiv[1] & clkdiv[2]) | (~clk1x_enable & 
   clkdiv[1] & clkdiv[2]) | (~clkdiv[0] & clkdiv[1] & clkdiv[2]) | (~clk1x_enable & 
   clkdiv[0] & clkdiv[1] & clkdiv[2]);
assign un1_clk1x_enable10_2_0 = (~no_bits_sent[0] & ~no_bits_sent[1]) | 
   (no_bits_sent[0] & no_bits_sent[1]) | (no_bits_sent[0] & ~no_bits_sent[2]) | 
   (~no_bits_sent[1] & ~no_bits_sent[2]) | (no_bits_sent[0] & no_bits_sent[1] & 
   ~no_bits_sent[2]) | (~no_bits_sent[0] & no_bits_sent[2]) | (~no_bits_sent[0] & 
   ~no_bits_sent[1] & no_bits_sent[2]) | (no_bits_sent[1] & no_bits_sent[2]) | 
   (no_bits_sent[0] & ~no_bits_sent[3]) | (~no_bits_sent[1] & ~no_bits_sent[3]) | 
   (no_bits_sent[0] & no_bits_sent[1] & ~no_bits_sent[3]) | (no_bits_sent[0] & 
   ~no_bits_sent[2] & ~no_bits_sent[3]) | (~no_bits_sent[1] & ~no_bits_sent[2] & 
   ~no_bits_sent[3]) | (no_bits_sent[0] & no_bits_sent[1] & ~no_bits_sent[2] & 
   ~no_bits_sent[3]) | (no_bits_sent[2] & ~no_bits_sent[3]) | (~no_bits_sent[0] & 
   no_bits_sent[3]) | (~no_bits_sent[0] & ~no_bits_sent[1] & no_bits_sent[3]) | 
   (no_bits_sent[1] & no_bits_sent[3]) | (~no_bits_sent[2] & no_bits_sent[3]) | 
   (~no_bits_sent[0] & no_bits_sent[2] & no_bits_sent[3]) | (~no_bits_sent[0] & 
   ~no_bits_sent[1] & no_bits_sent[2] & no_bits_sent[3]) | (no_bits_sent[1] & 
   no_bits_sent[2] & no_bits_sent[3]);
assign tsr_6[1] = (parity7 & tbr[1]) | (parity7 & tbr[1] & ~tsr[0]) | (~parity7 & 
   tsr[0]) | (~parity7 & ~tbr[1] & tsr[0]) | (tbr[1] & tsr[0]);
assign tsr_6[2] = (parity7 & tbr[2]) | (parity7 & tbr[2] & ~tsr[1]) | (~parity7 & 
   tsr[1]) | (~parity7 & ~tbr[2] & tsr[1]) | (tbr[2] & tsr[1]);
assign tsr_6[3] = (parity7 & tbr[3]) | (parity7 & tbr[3] & ~tsr[2]) | (~parity7 & 
   tsr[2]) | (~parity7 & ~tbr[3] & tsr[2]) | (tbr[3] & tsr[2]);
assign tsr_6[4] = (parity7 & tbr[4]) | (parity7 & tbr[4] & ~tsr[3]) | (~parity7 & 
   tsr[3]) | (~parity7 & ~tbr[4] & tsr[3]) | (tbr[4] & tsr[3]);
assign tsr_6[5] = (parity7 & tbr[5]) | (parity7 & tbr[5] & ~tsr[4]) | (~parity7 & 
   tsr[4]) | (~parity7 & ~tbr[5] & tsr[4]) | (tbr[5] & tsr[4]);
assign tsr_6[6] = (parity7 & tbr[6]) | (parity7 & tbr[6] & ~tsr[5]) | (~parity7 & 
   tsr[5]) | (~parity7 & ~tbr[6] & tsr[5]) | (tbr[6] & tsr[5]);
assign tsr_6[7] = (parity7 & tbr[7]) | (parity7 & tbr[7] & ~tsr[6]) | (~parity7 & 
   tsr[6]) | (~parity7 & ~tbr[7] & tsr[6]) | (tbr[7] & tsr[6]);
assign N_26_i = (no_bits_sent[0] & ~no_bits_sent[1] & ~no_bits_sent[2] & 
   ~no_bits_sent[3]) | (~no_bits_sent[0] & ~no_bits_sent[1] & no_bits_sent[2] & 
   no_bits_sent[3]);
assign no_bits_sent_n1_fast = (no_bits_sent[0] & ~no_bits_sent_fast[1]) | 
   (~no_bits_sent[0] & no_bits_sent_fast[1]);
assign N_24_i = (N_24_i_L1 & no_bits_sent_fast[0]) | (N_24_i_L1 & no_bits_sent_fast[0] & 
   ~no_bits_sent_fast[2]) | (N_24_i_L1 & no_bits_sent_fast[2]) | (no_bits_sent_fast[0] & 
   ~no_bits_sent_fast[3]) | (no_bits_sent_fast[0] & ~no_bits_sent_fast[2] & 
   ~no_bits_sent_fast[3]) | (no_bits_sent_fast[2] & ~no_bits_sent_fast[3]) | 
   (N_24_i_L1 & no_bits_sent_fast[3]);
assign N_24_i_L1 = (~no_bits_sent_0_rep1 & ~no_bits_sent_2_rep1) | (~no_bits_sent_2_rep1 & 
   ~no_bits_sent_fast[1]) | (~no_bits_sent_0_rep1 & ~no_bits_sent_2_rep1 & 
   no_bits_sent_fast[1]);
assign un1_clk1x_enable10_2_i = (~un1_clk1x_enable10_2_0) | (~un1_clk1x_enable10_2_0 & 
   ~wrn1) | (~un1_clk1x_enable10_2_0 & ~wrn2 & ~wrn1) | (wrn2 & ~wrn1) | 
   (~un1_clk1x_enable10_2_0 & wrn1);
//@6:42
  assign NN_1 = 1'b0;
  assign NN_2 = 1'b1;
endmodule /* txmit */

module uart (
  dout,
  data_ready,
  framing_error,
  parity_error,
  rxd,
  clk16x,
  rst,
  rdn,
  din,
  tbre,
  tsre,
  wrn,
  sdo
);
output [7:0] dout /* synthesis syn_tristate = 1 */;
output data_ready ;
output framing_error ;
output parity_error ;
input rxd ;
input clk16x ;
input rst ;
input rdn ;
input [7:0] din ;
output tbre ;
output tsre ;
input wrn ;
output sdo ;
wire data_ready ;
wire framing_error ;
wire parity_error ;
wire rxd ;
wire clk16x ;
wire rst ;
wire rdn ;
wire tbre ;
wire tsre ;
wire wrn ;
wire sdo ;
wire [3:0] \u2.no_bits_sent ;
wire [7:0] \u2.tbr ;
wire [7:7] \u2.tsr ;
wire [3:0] \u1.no_bits_rcvd ;
wire [7:0] \u1.rsr ;
wire [7:0] \u1.rbr ;
wire [3:3] \u1.clkdiv ;
wire [3:0] \u2.no_bits_sent_fast ;
wire [7:0] din_c;
wire [3:3] \u2.clkdiv_i_0 ;
wire \u2.parity  ;
wire \u2.parity9  ;
wire \u1.rxd1  ;
wire \u1.parity8  ;
wire N_25_a2 ;
wire un1_parity7_2 ;
wire \u1.parity7  ;
wire \u2.parity11  ;
wire \u2.un1_no_bits_sent_3_p4  ;
wire \u2.un3_p4  ;
wire \u2.un1_clk1x_enable10_2_i  ;
wire \u2.N_26_i  ;
wire \u2.N_21_i  ;
wire \u2.N_22_i  ;
wire \u2.N_23_i  ;
wire g0_2 ;
wire g0_7 ;
wire \u2.no_bits_sent_0_rep1  ;
wire \u2.no_bits_sent_2_rep1  ;
wire g0_7_x0 ;
wire GND ;
wire VCC ;
wire data_ready_c ;
wire framing_error_c ;
wire parity_error_c ;
wire rxd_c ;
wire clk16x_c ;
wire rst_c ;
wire rdn_c ;
wire tbre_c ;
wire tsre_c ;
wire wrn_c ;
wire sdo_c ;
wire GSRN ;
wire wrn_c_i ;
wire GND_Z ;
wire VCC_Z ;
  PUR PUR_INST (
	.PUR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
  INV wrn_c_i_cZ (
	.A(wrn_c),
	.Z(wrn_c_i)
);
// @4:83
  IFS1P3DX \u2_tbrio_Z[0]  (
	.D(din_c[0]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [0])
);
// @4:83
  IFS1P3DX \u2_tbrio_Z[1]  (
	.D(din_c[1]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [1])
);
// @4:83
  IFS1P3DX \u2_tbrio_Z[2]  (
	.D(din_c[2]),
	.SP(VCC),
	.SCLK(wrn_c_i),
	.CD(GND),
	.Q(\u2.tbr [2])
);