uart.vm

UART 串口程序

//
// Written by Synplify
// Synplify 9.0.0, Build 273R.
// Tue Jul 17 10:47:47 2007
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\program\isplever\synpbase\lib\lucent\xp.v "
// file 2 "\d:\program\isplever\ispcpld\..\cae_library\synthesis\verilog\xp.v "
// file 3 "\f:\custmo~1\codete~1\2\1\uart_v.h "
// file 4 "\f:\custmo~1\uart_verilog\txmit.v "
// file 5 "\f:\custmo~1\uart_verilog\rcvr.v "
// file 6 "\f:\custmo~1\uart_verilog\uart.v "

`timescale 100 ps/100 ps
module rcvr (
  rsr,
  clkdiv_3,
  no_bits_rcvd,
  un1_parity7_2,
  N_25_a2,
  rst_c,
  rdn_c,
  VCC,
  GSRN,
  clk16x_c,
  rxd1,
  GND,
  data_ready_c,
  parity7,
  parity8,
  parity_error_c
);
output [7:0] rsr ;
output clkdiv_3 ;
output [3:0] no_bits_rcvd ;
output un1_parity7_2 ;
output N_25_a2 ;
input rst_c ;
input rdn_c ;
input VCC ;
input GSRN ;
input clk16x_c ;
input rxd1 ;
input GND ;
output data_ready_c ;
input parity7 ;
output parity8 ;
output parity_error_c ;
wire clkdiv_3 ;
wire un1_parity7_2 ;
wire N_25_a2 ;
wire rst_c ;
wire rdn_c ;
wire VCC ;
wire GSRN ;
wire clk16x_c ;
wire rxd1 ;
wire GND ;
wire data_ready_c ;
wire parity7 ;
wire parity8 ;
wire parity_error_c ;
wire [7:0] rsr_QN;
wire [0:0] no_bits_rcvd_i;
wire [3:0] no_bits_rcvd_QN;
wire [3:0] clkdiv_QN_0;
wire [3:0] clkdiv_4;
wire [3:0] clkdiv;
wire rxd2_QN ;
wire fb ;
wire parity_error_QN ;
wire parity_QN_0 ;
wire fb_0 ;
wire data_ready_QN ;
wire clk1x_enable_QN_0 ;
wire parity_3 ;
wire no_bits_rcvd_n1 ;
wire clkdiv_4_p4 ;
wire N_30_i ;
wire N_31_i ;
wire no_bits_rcvd_n2 ;
wire data_ready9 ;
wire rxd2 ;
wire no_bits_rcvd_n3 ;
wire clk1x_enable ;
wire parity ;
wire clk1x_enable10 ;
wire un1_no_bits_rcvd_1_0 ;
wire N_29_i ;
wire NN_1 ;
wire NN_2 ;
  INV \no_bits_rcvd_i_cZ[0]  (
	.A(no_bits_rcvd[0]),
	.Z(no_bits_rcvd_i[0])
);
assign fb = (parity_error_c) | (parity_error_c & ~parity) | (parity_error_c & 
   ~parity7 & ~parity) | (~parity8 & ~parity7 & ~parity) | (parity_error_c & 
   parity8 & ~parity7 & ~parity) | (parity_error_c & parity7 & ~parity) | 
   (parity_error_c & parity);
assign fb_0 = (data_ready_c) | (data_ready_c & ~data_ready9) | (data_ready9);
// @5:52
  FD1S3AY rxd2_Z (
	.D(rxd1),
	.CK(clk16x_c),
	.Q(rxd2)
);
// @5:97
  FD1P3AX \rsr_Z[0]  (
	.D(rxd2),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[0])
);
// @5:97
  FD1P3AX \rsr_Z[1]  (
	.D(rsr[0]),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[1])
);
// @5:97
  FD1P3AX \rsr_Z[2]  (
	.D(rsr[1]),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[2])
);
// @5:97
  FD1P3AX \rsr_Z[3]  (
	.D(rsr[2]),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[3])
);
// @5:97
  FD1P3AX \rsr_Z[4]  (
	.D(rsr[3]),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[4])
);
// @5:97
  FD1P3AX \rsr_Z[5]  (
	.D(rsr[4]),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[5])
);
// @5:97
  FD1P3AX \rsr_Z[6]  (
	.D(rsr[5]),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[6])
);
// @5:97
  FD1P3AX \rsr_Z[7]  (
	.D(rsr[6]),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(rsr[7])
);
// @5:97
  FD1S3AX parity_error_Z (
	.D(fb),
	.CK(clkdiv[3]),
	.Q(parity_error_c)
);
// @5:97
  FD1P3AY parity_Z (
	.D(parity_3),
	.SP(parity7),
	.CK(clkdiv[3]),
	.Q(parity)
);
// @5:127
  FD1S3DX \no_bits_rcvd_Z[0]  (
	.D(no_bits_rcvd_i[0]),
	.CK(clkdiv[3]),
	.CD(N_31_i),
	.Q(no_bits_rcvd[0])
);
defparam \no_bits_rcvd_Z[0] .GSR="DISABLED";
// @5:127
  FD1S3DX \no_bits_rcvd_Z[1]  (
	.D(no_bits_rcvd_n1),
	.CK(clkdiv[3]),
	.CD(N_31_i),
	.Q(no_bits_rcvd[1])
);
defparam \no_bits_rcvd_Z[1] .GSR="DISABLED";
// @5:127
  FD1S3DX \no_bits_rcvd_Z[2]  (
	.D(no_bits_rcvd_n2),
	.CK(clkdiv[3]),
	.CD(N_31_i),
	.Q(no_bits_rcvd[2])
);
defparam \no_bits_rcvd_Z[2] .GSR="DISABLED";
// @5:127
  FD1S3DX \no_bits_rcvd_Z[3]  (
	.D(no_bits_rcvd_n3),
	.CK(clkdiv[3]),
	.CD(N_31_i),
	.Q(no_bits_rcvd[3])
);
defparam \no_bits_rcvd_Z[3] .GSR="DISABLED";
// @5:76
  FD1S3DX data_ready_Z (
	.D(fb_0),
	.CK(clk16x_c),
	.CD(N_30_i),
	.Q(data_ready_c)
);
defparam data_ready_Z.GSR="DISABLED";
// @5:87
  FD1S3AX \clkdiv_Z[0]  (
	.D(clkdiv_4[0]),
	.CK(clk16x_c),
	.Q(clkdiv[0])
);
// @5:87
  FD1S3AX \clkdiv_Z[1]  (
	.D(clkdiv_4[1]),
	.CK(clk16x_c),
	.Q(clkdiv[1])
);
// @5:87
  FD1S3AX \clkdiv_Z[2]  (
	.D(clkdiv_4[2]),
	.CK(clk16x_c),
	.Q(clkdiv[2])
);
// @5:87
  FD1S3AX \clkdiv_Z[3]  (
	.D(clkdiv_4[3]),
	.CK(clk16x_c),
	.Q(clkdiv[3])
);
// @5:66
  FD1P3AX clk1x_enable_Z (
	.D(clk1x_enable10),
	.SP(N_29_i),
	.CK(clk16x_c),
	.Q(clk1x_enable)
);
assign clkdiv_4_p4 = (clk1x_enable & clkdiv[0] & clkdiv[1] & clkdiv[2]);
assign parity_3 = (parity & ~rsr[7]) | (~parity & rsr[7]);
assign clk1x_enable10 = (~rxd1 & rxd2);
assign no_bits_rcvd_n1 = (no_bits_rcvd[0] & ~no_bits_rcvd[1]) | (~no_bits_rcvd[0] & 
   no_bits_rcvd[1]);
assign clkdiv_4[0] = (clk1x_enable & ~clkdiv[0]) | (~clk1x_enable & clkdiv[0]);
assign clkdiv_4[3] = (clkdiv[3] & ~clkdiv_4_p4) | (~clkdiv[3] & clkdiv_4_p4);
assign un1_no_bits_rcvd_1_0 = (~no_bits_rcvd[1] & no_bits_rcvd[2]);
assign N_30_i = (~rdn_c) | (~rdn_c & ~rst_c) | (rst_c);
assign N_31_i = (rst_c) | (~clk1x_enable) | (rst_c & clk1x_enable);
assign no_bits_rcvd_n2 = (no_bits_rcvd[0] & no_bits_rcvd[1] & ~no_bits_rcvd[2]) | 
   (~no_bits_rcvd[0] & no_bits_rcvd[2]) | (~no_bits_rcvd[1] & no_bits_rcvd[2]) | 
   (~no_bits_rcvd[0] & no_bits_rcvd[1] & no_bits_rcvd[2]);
assign clkdiv_4[1] = (clk1x_enable & clkdiv[0] & ~clkdiv[1]) | (~clk1x_enable & 
   clkdiv[1]) | (~clkdiv[0] & clkdiv[1]) | (~clk1x_enable & clkdiv[0] & 
   clkdiv[1]);
assign parity8 = (~no_bits_rcvd[0] & no_bits_rcvd[1] & ~no_bits_rcvd[2] & 
   no_bits_rcvd[3]);
assign data_ready9 = (no_bits_rcvd[0] & no_bits_rcvd[1] & ~no_bits_rcvd[2] & 
   no_bits_rcvd[3]);
assign N_25_a2 = (no_bits_rcvd[1] & ~no_bits_rcvd[2] & no_bits_rcvd[3] & 
   ~rxd2);
assign no_bits_rcvd_n3 = (no_bits_rcvd[0] & no_bits_rcvd[1] & no_bits_rcvd[2] & 
   ~no_bits_rcvd[3]) | (~no_bits_rcvd[0] & no_bits_rcvd[3]) | (~no_bits_rcvd[1] & 
   no_bits_rcvd[3]) | (~no_bits_rcvd[0] & no_bits_rcvd[1] & no_bits_rcvd[3]) | 
   (~no_bits_rcvd[2] & no_bits_rcvd[3]) | (~no_bits_rcvd[0] & no_bits_rcvd[2] & 
   no_bits_rcvd[3]) | (~no_bits_rcvd[1] & no_bits_rcvd[2] & no_bits_rcvd[3]) | 
   (~no_bits_rcvd[0] & no_bits_rcvd[1] & no_bits_rcvd[2] & no_bits_rcvd[3]);
assign clkdiv_4[2] = (clk1x_enable & clkdiv[0] & clkdiv[1] & ~clkdiv[2]) | 
   (~clk1x_enable & clkdiv[2]) | (~clkdiv[0] & clkdiv[2]) | (~clk1x_enable & 
   clkdiv[0] & clkdiv[2]) | (~clkdiv[1] & clkdiv[2]) | (~clk1x_enable & 
   clkdiv[1] & clkdiv[2]) | (~clkdiv[0] & clkdiv[1] & clkdiv[2]) | (~clk1x_enable & 
   clkdiv[0] & clkdiv[1] & clkdiv[2]);
assign un1_parity7_2 = (parity & ~parity7 & ~parity8);
assign N_29_i = (clk1x_enable10) | (clk1x_enable10 & ~un1_no_bits_rcvd_1_0) | 
   (clk1x_enable10 & un1_no_bits_rcvd_1_0) | (clk1x_enable10 & ~no_bits_rcvd[3] & 
   un1_no_bits_rcvd_1_0) | (clk1x_enable10 & no_bits_rcvd[3] & un1_no_bits_rcvd_1_0) | 
   (~no_bits_rcvd[0] & no_bits_rcvd[3] & un1_no_bits_rcvd_1_0) | (clk1x_enable10 & 
   no_bits_rcvd[0] & no_bits_rcvd[3] & un1_no_bits_rcvd_1_0);
//@6:40
  assign NN_1 = 1'b0;
  assign NN_2 = 1'b1;
assign clkdiv_3 = clkdiv[3];
endmodule /* rcvr */

module txmit (
  tbr,
  tsr_7,
  no_bits_sent_fast,
  no_bits_sent,
  clkdiv_i_0,
  un1_clk1x_enable10_2_i,
  N_26_i,
  rst_c,
  VCC,
  parity,
  parity9,
  wrn_c,
  GSRN,
  clk16x_c,
  N_21_i,
  GND,
  no_bits_sent_2_rep1,
  no_bits_sent_0_rep1
);
input [7:0] tbr ;
output tsr_7 ;
output [3:0] no_bits_sent_fast ;
output [3:0] no_bits_sent ;
output [3:3] clkdiv_i_0 ;
output un1_clk1x_enable10_2_i ;
output N_26_i ;
input rst_c ;
input VCC ;
output parity ;
input parity9 ;
input wrn_c ;
input GSRN ;
input clk16x_c ;
output N_21_i ;
input GND ;
output no_bits_sent_2_rep1 ;
output no_bits_sent_0_rep1 ;
wire tsr_7 ;
wire un1_clk1x_enable10_2_i ;
wire N_26_i ;
wire rst_c ;
wire VCC ;
wire parity ;
wire parity9 ;
wire wrn_c ;
wire GSRN ;
wire clk16x_c ;
wire N_21_i ;
wire GND ;
wire no_bits_sent_2_rep1 ;
wire no_bits_sent_0_rep1 ;
wire [7:0] tsr_QN;
wire [0:0] no_bits_sent_i;
wire [3:0] no_bits_sent_QN;
wire [0:0] no_bits_sent_fast_i;
wire [3:0] no_bits_sent_fast_QN;
wire [3:0] clkdiv_QN;
wire [3:0] clkdiv_4;
wire [7:0] tsr_6;
wire [3:0] clkdiv;
wire [6:0] tsr;
wire wrn2_QN ;
wire wrn1_QN ;
wire parity_QN ;
wire no_bits_sent_n2_rep1 ;
wire no_bits_sent_2_rep1_QN ;
wire no_bits_sent_0_rep1_i ;
wire no_bits_sent_0_rep1_QN ;
wire no_bits_sent_n2_fast ;
wire no_bits_sent_n2 ;
wire no_bits_sent_n3_fast ;
wire no_bits_sent_n3 ;
wire un1_clk1x_enable11 ;
wire clk1x_enable_QN ;
wire no_bits_sent_n1 ;
wire clk1x_enable10 ;
wire parity_3 ;
wire clkdiv_4_p4 ;
wire N_27_i ;
wire clk1x_enable ;
wire parity7 ;
wire no_bits_sent_n1_fast ;
wire N_24_i ;
wire N_24_i_L1 ;
wire un1_clk1x_enable10_2_0 ;
wire wrn2 ;
wire wrn1 ;
wire NN_1 ;
wire NN_2 ;
  INV \clkdiv_i_cZ[3]  (
	.A(clkdiv[3]),
	.Z(clkdiv_i_0[3])
);
  INV \no_bits_sent_i_cZ[0]  (
	.A(no_bits_sent[0]),
	.Z(no_bits_sent_i[0])
);
  INV \no_bits_sent_fast_i_cZ[0]  (
	.A(no_bits_sent_fast[0]),
	.Z(no_bits_sent_fast_i[0])
);
  INV no_bits_sent_0_rep1_i_cZ (
	.A(no_bits_sent_0_rep1),
	.Z(no_bits_sent_0_rep1_i)
);
assign no_bits_sent_n3_fast = (no_bits_sent_fast[3] & ~no_bits_sent[2]) | 
   (no_bits_sent_fast[3] & ~no_bits_sent[1]) | (no_bits_sent_fast[3] & 
   ~no_bits_sent[2] & no_bits_sent[1]) | (no_bits_sent_fast[3] & ~no_bits_sent[0]) | 
   (no_bits_sent_fast[3] & ~no_bits_sent[2] & no_bits_sent[0]) | (no_bits_sent_fast[3] &