uart_v.mrp

UART 串口程序

Signal u2/clkdiv_4_pZ0Z4 - Driver Comp: u2/SLICE_39:O0
   Load Comps: u2/SLICE_16:I7
Signal rst_c - Driver Comp: rst:O0
   Load Comps: u2/SLICE_40:I0, u1/SLICE_41:I1, u1/SLICE_42:I0, GSR_INST:GSR
Signal u2/parityZ0Z7 - Driver Comp: u2/SLICE_29:O1
   Load Comps: u2/SLICE_17:I0, u2/SLICE_17:I6, u2/SLICE_18:I0, u2/SLICE_18:I6,
        u2/SLICE_19:I0, u2/SLICE_19:I6, u2/SLICE_20:I0, u2/SLICE_29:I0
Signal u2_tbr_0 - Driver Comp: din_0_MGIOL:O3
   Load Comps: u2/SLICE_17:I1
Signal u2_tbr_1 - Driver Comp: din_1_MGIOL:O3
   Load Comps: u2/SLICE_17:I7
Signal u2_tbr_2 - Driver Comp: din_2_MGIOL:O3
   Load Comps: u2/SLICE_18:I1
Signal u2_tbr_3 - Driver Comp: din_3_MGIOL:O3
   Load Comps: u2/SLICE_18:I7
Signal u2_tbr_4 - Driver Comp: din_4_MGIOL:O3
   Load Comps: u2/SLICE_19:I1
Signal u2_tbr_5 - Driver Comp: din_5_MGIOL:O3
   Load Comps: u2/SLICE_19:I7
Signal u2_tbr_6 - Driver Comp: din_6_MGIOL:O3
   Load Comps: u2/SLICE_20:I1
Signal u2_N_26_i - Driver Comp: SLICE_37:O0
   Load Comps: tsre_MGIOL:I3
Signal u2/N_24_i_LZ0Z1 - Driver Comp: u2/SLICE_32:O1
   Load Comps: u2/SLICE_32:I0
Signal u2_un1_clk1x_enable10_2_i - Driver Comp: u2/SLICE_25:O1
   Load Comps: tbre_MGIOL:I3
Signal u1/fb_0 - Driver Comp: u1/SLICE_0:O0
   Load Comps: u1/SLICE_0:I12
Signal u1/N_30_iZ0 - Driver Comp: u1/SLICE_41:O0

                                    Page 8




Design:  uart                                          Date:  07/17/07  10:48:27

Signal Cross Reference (cont)
-----------------------------
   Load Comps: u1/SLICE_0:I16
Signal u1/rxdZ0Z2 - Driver Comp: u1/SLICE_43:O3
   Load Comps: u1/SLICE_2:I1, u1/SLICE_10:I4, u1/SLICE_43:I3
Signal u1/clkdiv_4_3 - Driver Comp: u1/SLICE_7:O0
   Load Comps: u1/SLICE_7:I12
Signal u1/parityZ0Z_3 - Driver Comp: u1/SLICE_5:O0
   Load Comps: u1/SLICE_5:I12
Signal u1_parity7 - Driver Comp: SLICE_34:O1
   Load Comps: u1/SLICE_1:I2, u1/SLICE_5:I14, u1/SLICE_10:I14, u1/SLICE_11:I14,
        u1/SLICE_12:I14, u1/SLICE_13:I14, SLICE_34:I1
Signal u1/parityZ0 - Driver Comp: u1/SLICE_5:O3
   Load Comps: u1/SLICE_1:I3, u1/SLICE_5:I0, SLICE_34:I0
Signal u1/clk1x_enableZ0Z10 - Driver Comp: u1/SLICE_2:O0
   Load Comps: u1/SLICE_2:I12, u1/SLICE_33:I6
Signal u1/N_29_iZ0 - Driver Comp: u1/SLICE_33:O1
   Load Comps: u1/SLICE_2:I14
Signal u1/clk1x_enableZ0 - Driver Comp: u1/SLICE_2:O3
   Load Comps: u1/SLICE_3:I0, u1/SLICE_3:I6, u1/SLICE_4:I0, u1/SLICE_7:I6,
        u1/SLICE_42:I1
Signal parity_error_c - Driver Comp: u1/SLICE_1:O3
   Load Comps: u1/SLICE_1:I0, parity_error:I0
Signal u1_parity8 - Driver Comp: u1/SLICE_1:O1
   Load Comps: u1/SLICE_1:I1, SLICE_34:I2, dout_0_MGIOL:I3, dout_7_MGIOL:I3,
        dout_6_MGIOL:I3, dout_5_MGIOL:I3, dout_4_MGIOL:I3, dout_3_MGIOL:I3,
        dout_2_MGIOL:I3, dout_1_MGIOL:I3
Signal u1/fb - Driver Comp: u1/SLICE_1:O0
   Load Comps: u1/SLICE_1:I12
Signal u1/data_readyZ0Z9 - Driver Comp: u1/SLICE_0:O1
   Load Comps: u1/SLICE_0:I1
Signal u1_rsr_0 - Driver Comp: u1/SLICE_10:O3
   Load Comps: u1/SLICE_10:I5, dout_0_MGIOL:I8
Signal u1_rsr_1 - Driver Comp: u1/SLICE_10:O4
   Load Comps: u1/SLICE_11:I4, dout_1_MGIOL:I8
Signal u1_rsr_2 - Driver Comp: u1/SLICE_11:O3
   Load Comps: u1/SLICE_11:I5, dout_2_MGIOL:I8
Signal u1_rsr_3 - Driver Comp: u1/SLICE_11:O4
   Load Comps: u1/SLICE_12:I4, dout_3_MGIOL:I8
Signal u1_rsr_4 - Driver Comp: u1/SLICE_12:O3
   Load Comps: u1/SLICE_12:I5, dout_4_MGIOL:I8
Signal u1_rsr_5 - Driver Comp: u1/SLICE_12:O4
   Load Comps: u1/SLICE_13:I4, dout_5_MGIOL:I8
Signal u1_rsr_6 - Driver Comp: u1/SLICE_13:O3
   Load Comps: u1/SLICE_13:I5, dout_6_MGIOL:I8
Signal u1_rsr_7 - Driver Comp: u1/SLICE_13:O4
   Load Comps: u1/SLICE_5:I1, dout_7_MGIOL:I8
Signal u1/no_bits_rcvd_iZ0Z_0 - Driver Comp: u1/SLICE_8:O0
   Load Comps: u1/SLICE_8:I12
Signal u1/N_31_iZ0 - Driver Comp: u1/SLICE_42:O0
   Load Comps: u1/SLICE_8:I16, u1/SLICE_9:I16
Signal u1_no_bits_rcvd_0 - Driver Comp: u1/SLICE_8:O3
   Load Comps: u1/SLICE_0:I6, u1/SLICE_1:I6, u1/SLICE_8:I0, u1/SLICE_8:I6,
        u1/SLICE_9:I0, u1/SLICE_9:I6, u1/SLICE_33:I7, SLICE_34:I6
Signal u1/no_bits_rcvd_nZ0Z1 - Driver Comp: u1/SLICE_8:O1
   Load Comps: u1/SLICE_8:I13
Signal u1_no_bits_rcvd_1 - Driver Comp: u1/SLICE_8:O4
   Load Comps: u1/SLICE_0:I7, u1/SLICE_1:I7, u1/SLICE_8:I7, u1/SLICE_9:I1,

                                    Page 9




Design:  uart                                          Date:  07/17/07  10:48:27

Signal Cross Reference (cont)
-----------------------------
        u1/SLICE_9:I7, u1/SLICE_33:I0, SLICE_34:I7, u1/SLICE_43:I0
Signal u1/no_bits_rcvd_nZ0Z2 - Driver Comp: u1/SLICE_9:O0
   Load Comps: u1/SLICE_9:I12
Signal u1_no_bits_rcvd_2 - Driver Comp: u1/SLICE_9:O3
   Load Comps: u1/SLICE_0:I8, u1/SLICE_1:I8, u1/SLICE_9:I2, u1/SLICE_9:I8,
        u1/SLICE_33:I1, SLICE_34:I8, u1/SLICE_43:I1
Signal u1/no_bits_rcvd_nZ0Z3 - Driver Comp: u1/SLICE_9:O1
   Load Comps: u1/SLICE_9:I13
Signal u1_no_bits_rcvd_3 - Driver Comp: u1/SLICE_9:O4
   Load Comps: u1/SLICE_0:I9, u1/SLICE_1:I9, u1/SLICE_9:I9, u1/SLICE_33:I8,
        SLICE_34:I9, u1/SLICE_43:I2
Signal u1/clkdiv_4_0 - Driver Comp: u1/SLICE_3:O0
   Load Comps: u1/SLICE_3:I12
Signal u1/clkdivZ0Z_0 - Driver Comp: u1/SLICE_3:O3
   Load Comps: u1/SLICE_3:I1, u1/SLICE_3:I7, u1/SLICE_4:I1, u1/SLICE_7:I7
Signal u1/clkdiv_4_1 - Driver Comp: u1/SLICE_3:O1
   Load Comps: u1/SLICE_3:I13
Signal u1/clkdivZ0Z_1 - Driver Comp: u1/SLICE_3:O4
   Load Comps: u1/SLICE_3:I8, u1/SLICE_4:I2, u1/SLICE_7:I8
Signal u1/clkdiv_4_2 - Driver Comp: u1/SLICE_4:O0
   Load Comps: u1/SLICE_4:I12
Signal u1/clkdivZ0Z_2 - Driver Comp: u1/SLICE_4:O3
   Load Comps: u1/SLICE_4:I3, u1/SLICE_7:I9
Signal u1/clkdiv_4_pZ0Z4 - Driver Comp: u1/SLICE_7:O1
   Load Comps: u1/SLICE_7:I1
Signal u1/un1_no_bits_rcvd_1Z0Z_0 - Driver Comp: u1/SLICE_33:O0
   Load Comps: u1/SLICE_33:I9
Signal din_c_0 - Driver Comp: din_0:O0
   Load Comps: din_0_MGIOL:I0
Signal din_c_1 - Driver Comp: din_1:O0
   Load Comps: din_1_MGIOL:I0
Signal din_c_2 - Driver Comp: din_2:O0
   Load Comps: din_2_MGIOL:I0
Signal din_c_3 - Driver Comp: din_3:O0
   Load Comps: din_3_MGIOL:I0
Signal din_c_4 - Driver Comp: din_4:O0
   Load Comps: din_4_MGIOL:I0
Signal din_c_5 - Driver Comp: din_5:O0
   Load Comps: din_5_MGIOL:I0
Signal din_c_6 - Driver Comp: din_6:O0
   Load Comps: din_6_MGIOL:I0
Signal tsre_c - Driver Comp: tsre_MGIOL:O0
   Load Comps: tsre:I1
Signal tbre_c - Driver Comp: tbre_MGIOL:O0
   Load Comps: tbre:I1
Signal u1_rbr_1 - Driver Comp: dout_1_MGIOL:O0
   Load Comps: dout_1:I1
Signal u1_rbr_2 - Driver Comp: dout_2_MGIOL:O0
   Load Comps: dout_2:I1
Signal u1_rbr_3 - Driver Comp: dout_3_MGIOL:O0
   Load Comps: dout_3:I1
Signal u1_rbr_4 - Driver Comp: dout_4_MGIOL:O0
   Load Comps: dout_4:I1
Signal u1_rbr_5 - Driver Comp: dout_5_MGIOL:O0
   Load Comps: dout_5:I1
Signal u1_rbr_6 - Driver Comp: dout_6_MGIOL:O0

                                   Page 10




Design:  uart                                          Date:  07/17/07  10:48:27

Signal Cross Reference (cont)
-----------------------------
   Load Comps: dout_6:I1
Signal u1_rbr_7 - Driver Comp: dout_7_MGIOL:O0
   Load Comps: dout_7:I1
Signal u2_un1_no_bits_sent_3_p4 - Driver Comp: SLICE_35:O0
   Load Comps: SLICE_35:I8
Signal g0Z0Z_2 - Driver Comp: SLICE_37:O1
   Load Comps: SLICE_35:I6
Signal u2_un3_p4 - Driver Comp: SLICE_24:O1
   Load Comps: SLICE_35:I9
Signal u2_parity11 - Driver Comp: SLICE_36:O0
   Load Comps: SLICE_35:I7, SLICE_36:I8

PGROUP Utilization
------------------

Run Time and Memory Usage
------------------------- 
Total CPU Time: 0 secs  
Total REAL Time: 2 secs
Peak Memory Usage: 25 MB







































                                   Page 11


Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995
     AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent
     Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems
     All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor
     Corporation,  All rights reserved.