uart_v.mrp

UART 串口程序

                Lattice Mapping Report File for Design 'uart'

Design Information
------------------

Command line:   D:\program\isplever\ispfpga\bin\nt\map.exe -a mg5g00 -p LFXP3C
     -t TQFP100 -s 3 uart_v.ngd -o uart_v_map.ncd -mp uart_v.mrp uart_v.lpf
Target Vendor:  LATTICE
Target Device:  LFXP3CTQFP100
Target Speed:   3
Mapper:  mg5g00,  version:  ispLever_v61_PROD_Build (37)
Mapped on:  07/17/07  10:48:27

Design Summary
--------------

   Number of registers:    68
      PFU registers:    47
      PIO registers:    21
   Number of SLICEs:            43 out of  1536 (3%)
      SLICEs(logic/ROM):        43 out of  1152 (4%)
      SLICEs(logic/ROM/RAM):     0 out of   384 (0%)
          As RAM:            0
          As Logic/ROM:      0
   Number of logic LUT4s:      65
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:      0 (0 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:      65
   Number of external PIOs: 27 out of 62 (44%)
   Number of PIO IDDR/ODDR:     0
   Number of PIO FIXEDDELAY:    0
   Number of 3-state buffers:   0
   Number of PLLs:  0 out of 2 (0%)
   Number of block RAMs:  0 out of 6 (0%)
   Number of GSRs:  1 out of 1 (100%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  4
     Net u1_clkdiv_3: 17 loads, 17 rising, 0 falling (Driver: u1/clkdivZ0Z_3 )
     Net clk16x_c: 12 loads, 12 rising, 0 falling (Driver: PIO clk16x )
     Net wrn_c: 8 loads, 8 rising, 0 falling (Driver: PIO wrn )
     Net u2/clkdivZ0Z_3: 14 loads, 8 rising, 6 falling (Driver: u2/clkdiv_3 )
   Number of Clock Enables:  10
     Net un1_parity7_2: 1 loads, 0 LSLICEs
     Net u2_N_23_i: 1 loads, 0 LSLICEs
     Net u2/un1_clk1x_enableZ0Z11: 1 loads, 1 LSLICEs
     Net u2/N_24_iZ0: 5 loads, 5 LSLICEs
     Net u2_parity9: 1 loads, 1 LSLICEs
     Net u2_N_26_i: 1 loads, 0 LSLICEs
     Net u2_un1_clk1x_enable10_2_i: 1 loads, 0 LSLICEs
     Net u1_parity7: 5 loads, 5 LSLICEs
     Net u1/N_29_iZ0: 1 loads, 1 LSLICEs

                                    Page 1




Design:  uart                                          Date:  07/17/07  10:48:27

Design Summary (cont)
---------------------
     Net u1_parity8: 8 loads, 0 LSLICEs
   Number of LSRs:  3
     Net u2/N_27_iZ0: 6 loads, 6 LSLICEs
     Net u1/N_30_iZ0: 1 loads, 1 LSLICEs
     Net u1/N_31_iZ0: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net u2_no_bits_sent_0: 12 loads
     Net u2_no_bits_sent_1: 11 loads
     Net u1_parity8: 10 loads
     Net rdn_c: 9 loads
     Net u1_no_bits_rcvd_0: 8 loads
     Net u1_no_bits_rcvd_1: 8 loads
     Net u2/parityZ0Z7: 8 loads
     Net u2_no_bits_sent_2: 8 loads
     Net u1_parity7: 7 loads
     Net u2_no_bits_sent_3: 7 loads

IO (PIO) Attributes
-------------------

+---------------------+-----------+-----------+------------+------------+
| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
|                     |           |  IO_TYPE  | Register   |            |
+---------------------+-----------+-----------+------------+------------+
| dout_0              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| data_ready          | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| rxd                 | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| sdo                 | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| wrn                 | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| tsre                | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| tbre                | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| din_7               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| din_6               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| din_5               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| din_4               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| din_3               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| din_2               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| din_1               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| din_0               | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| rdn                 | INPUT     | LVCMOS25  |            |            |

                                    Page 2




Design:  uart                                          Date:  07/17/07  10:48:27

IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+------------+
| rst                 | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| clk16x              | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| parity_error        | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| framing_error       | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| dout_7              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| dout_6              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| dout_5              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| dout_4              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| dout_3              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| dout_2              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| dout_1              | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+

Removed logic
-------------

Block GND_0 undriven or does not drive anything - clipped.
Block VCC_0 undriven or does not drive anything - clipped.
Signal wrn_c_iZ0 was merged into signal wrn_c
Signal GSRNZ0 was merged into signal rst_c
Signal u2_clkdiv_i_0_3 was merged into signal u2/clkdivZ0Z_3
Signal GNDZ0 undriven or does not drive anything - clipped.
Signal VCCZ0 undriven or does not drive anything - clipped.
Block wrn_c_i was optimized away.
Block GSRN was optimized away.
Block u2/clkdiv_i_3 was optimized away.

Symbol Cross Reference
----------------------

u1/SLICE_0 (PFU) covers blocks: u1/data_ready_fb, u1/data_ready9, u1/data_ready
u1/SLICE_1 (PFU) covers blocks: u1/parity_error_fb, u1/parityZ0Z8,
     u1/parity_error
u1/SLICE_2 (PFU) covers blocks: u1/clk1x_enable10, u1/clk1x_enable
u1/SLICE_3 (PFU) covers blocks: u1/clkdiv_4_axbxc0, u1/clkdiv_4_axbxc1,
     u1/clkdiv_0, u1/clkdiv_1
u1/SLICE_4 (PFU) covers blocks: u1/clkdiv_4_axbxc2, u1/clkdiv_2
u1/SLICE_5 (PFU) covers blocks: u1/parity_3, u1/parity
u1/SLICE_7 (PFU) covers blocks: u1/clkdiv_4_axbxc3, u1/clkdiv_4_p4,
     u1/clkdivZ0Z_3
u1/SLICE_8 (PFU) covers blocks: u1/no_bits_rcvd_i_0, u1/no_bits_rcvd_n1,
     u1/no_bits_rcvdZ0Z_0, u1/no_bits_rcvdZ0Z_1
u1/SLICE_9 (PFU) covers blocks: u1/no_bits_rcvd_n2, u1/no_bits_rcvd_n3,
     u1/no_bits_rcvdZ0Z_2, u1/no_bits_rcvdZ0Z_3
u1/SLICE_10 (PFU) covers blocks: u1/rsrZ0Z_0, u1/rsrZ0Z_1

                                    Page 3




Design:  uart                                          Date:  07/17/07  10:48:27

Symbol Cross Reference (cont)
-----------------------------
u1/SLICE_11 (PFU) covers blocks: u1/rsrZ0Z_2, u1/rsrZ0Z_3
u1/SLICE_12 (PFU) covers blocks: u1/rsrZ0Z_4, u1/rsrZ0Z_5
u1/SLICE_13 (PFU) covers blocks: u1/rsrZ0Z_6, u1/rsrZ0Z_7
u2/SLICE_14 (PFU) covers blocks: u2/N_19_a3, u2/clk1x_enable
u2/SLICE_15 (PFU) covers blocks: u2/clkdiv_4_axbxc0, u2/clkdiv_4_axbxc1,
     u2/clkdiv_0, u2/clkdiv_1
u2/SLICE_16 (PFU) covers blocks: u2/clkdiv_4_axbxc2, u2/clkdiv_4_axbxc3,
     u2/clkdiv_2, u2/clkdiv_3
u2/SLICE_17 (PFU) covers blocks: u2/tsr_6_0, u2/tsr_6_0_1, u2/tsr_0, u2/tsr_1
u2/SLICE_18 (PFU) covers blocks: u2/tsr_6_0_2, u2/tsr_6_0_3, u2/tsr_2, u2/tsr_3
u2/SLICE_19 (PFU) covers blocks: u2/tsr_6_0_4, u2/tsr_6_0_5, u2/tsr_4, u2/tsr_5
u2/SLICE_20 (PFU) covers blocks: u2/tsr_6_0_6, u2/tsr_6
u2/SLICE_21 (PFU) covers blocks: u2/wrn1, u2/wrn2
u2/SLICE_22 (PFU) covers blocks: u2/no_bits_sent_i_0, u2/no_bits_sent_n1,
     u2/no_bits_sentZ0Z_0, u2/no_bits_sentZ0Z_1
u2/SLICE_23 (PFU) covers blocks: u2/no_bits_sent_n2, u2/no_bits_sent_n3,
     u2/no_bits_sentZ0Z_2, u2/no_bits_sentZ0Z_3
SLICE_24 (PFU) covers blocks: u2/no_bits_sent_0_rep1_i, g0_4,
     u2/no_bits_sent_0_repZ0Z1
u2/SLICE_25 (PFU) covers blocks: u2/no_bits_sent_n2_rep1,
     u2/un1_clk1x_enable10_2_iZ0, u2/no_bits_sent_2_repZ0Z1
u2/SLICE_26 (PFU) covers blocks: u2/no_bits_sent_fast_i_0,
     u2/no_bits_sent_n1_fast, u2/no_bits_sent_fastZ0Z_0,
     u2/no_bits_sent_fastZ0Z_1
u2/SLICE_27 (PFU) covers blocks: u2/no_bits_sent_n2_fast,
     u2/no_bits_sent_n3_fast, u2/no_bits_sent_fastZ0Z_2,
     u2/no_bits_sent_fastZ0Z_3
SLICE_28 (PFU) covers blocks: u2/parity_3, g0_6, u2/parityZ0
u2/SLICE_29 (PFU) covers blocks: u2/tsr_6_0_7, u2/parity7, u2/tsrZ0Z_7
u2/SLICE_30 (PFU) covers blocks: u2/un1_clk1x_enable11,
     u2/un1_clk1x_enable10_2_0
SLICE_31 (PFU) covers blocks: g0_7, g0_7_x0
u2/SLICE_32 (PFU) covers blocks: u2/N_24_i, u2/N_24_i_L1
u1/SLICE_33 (PFU) covers blocks: u1/un1_no_bits_rcvd_1_0, u1/N_29_i
SLICE_34 (PFU) covers blocks: u1/un1_parity7Z0Z_2, g0_0
SLICE_35 (PFU) covers blocks: g0_1, g0
SLICE_36 (PFU) covers blocks: g0_5, g0_8
SLICE_37 (PFU) covers blocks: u2/N_26_iZ0, g0_2
u2/SLICE_38 (PFU) covers blocks: u2/N_21_iZ0
u2/SLICE_39 (PFU) covers blocks: u2/clkdiv_4_p4
u2/SLICE_40 (PFU) covers blocks: u2/N_27_i
u1/SLICE_41 (PFU) covers blocks: u1/N_30_i
u1/SLICE_42 (PFU) covers blocks: u1/N_31_i
u1/SLICE_43 (PFU) covers blocks: u1/N_25_aZ0Z2, u1/rxd2