uart.vhm

UART 串口程序

      GSRN : in std_logic;
      clk16x_c : in std_logic;
      rxd1 : in std_logic;
      GND : in std_logic;
      data_ready_c : out std_logic;
      parity7 : in std_logic;
      parity8 : out std_logic;
      parity_error_c : out std_logic  );
  end component;
  component txmit
    port(
      tbr : in std_logic_vector(7 downto 0);
      tsr_7 : out std_logic;
      no_bits_sent_fast : out std_logic_vector(3 downto 0);
      no_bits_sent : out std_logic_vector(3 downto 0);
      clkdiv_i_0 : out std_logic_vector(3 downto 3);
      un1_clk1x_enable10_2_i : out std_logic;
      N_26_i : out std_logic;
      rst_c : in std_logic;
      VCC : in std_logic;
      parity : out std_logic;
      parity9 : in std_logic;
      wrn_c : in std_logic;
      GSRN : in std_logic;
      clk16x_c : in std_logic;
      N_21_i : out std_logic;
      GND : in std_logic;
      no_bits_sent_2_rep1 : out std_logic;
      no_bits_sent_0_rep1 : out std_logic  );
  end component;
begin
  II_PUR_INST: PUR port map (
      PUR => VCC);
  II_VCC_0: VHI port map (
      Z => VCC);
  II_GND_0: VLO port map (
      Z => GND);
  II_wrn_c_i: INV port map (
      A => WRN_C,
      Z => WRN_C_I);
  \II_u2_tbrio[0]\: IFS1P3DX port map (
      D => DIN_C(0),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(0));
  \II_u2_tbrio[1]\: IFS1P3DX port map (
      D => DIN_C(1),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(1));
  \II_u2_tbrio[2]\: IFS1P3DX port map (
      D => DIN_C(2),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(2));
  \II_u2_tbrio[3]\: IFS1P3DX port map (
      D => DIN_C(3),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(3));
  \II_u2_tbrio[4]\: IFS1P3DX port map (
      D => DIN_C(4),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(4));
  \II_u2_tbrio[5]\: IFS1P3DX port map (
      D => DIN_C(5),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(5));
  \II_u2_tbrio[6]\: IFS1P3DX port map (
      D => DIN_C(6),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(6));
  \II_u2_tbrio[7]\: IFS1P3DX port map (
      D => DIN_C(7),
      SP => VCC,
      SCLK => WRN_C_I,
      CD => GND,
      Q => \U2.TBR\(7));
  II_u1_rxd1io: IFS1P3BX port map (
      D => RXD_C,
      SP => VCC,
      SCLK => CLK16X_C,
      PD => GND,
      Q => \U1.RXD1\);
  II_u2_tsreio: OFS1P3BX port map (
      D => \U2.NO_BITS_SENT\(2),
      SP => \U2.N_26_I\,
      SCLK => \U2.CLKDIV_I_0\(3),
      PD => GND,
      Q => TSRE_C);
  II_u2_tbreio: OFS1P3DX port map (
      D => \U2.N_21_I\,
      SP => \U2.UN1_CLK1X_ENABLE10_2_I\,
      SCLK => CLK16X_C,
      CD => GND,
      Q => TBRE_C);
  II_u2_sdoio: OFS1P3BX port map (
      D => \U2.N_22_I\,
      SP => \U2.N_23_I\,
      SCLK => \U2.CLKDIV_I_0\(3),
      PD => GND,
      Q => SDO_C);
  \II_u1_rbrio[0]\: OFS1P3DX port map (
      D => \U1.RSR\(0),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(0));
  \II_u1_rbrio[1]\: OFS1P3DX port map (
      D => \U1.RSR\(1),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(1));
  \II_u1_rbrio[2]\: OFS1P3DX port map (
      D => \U1.RSR\(2),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(2));
  \II_u1_rbrio[3]\: OFS1P3DX port map (
      D => \U1.RSR\(3),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(3));
  \II_u1_rbrio[4]\: OFS1P3DX port map (
      D => \U1.RSR\(4),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(4));
  \II_u1_rbrio[5]\: OFS1P3DX port map (
      D => \U1.RSR\(5),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(5));
  \II_u1_rbrio[6]\: OFS1P3DX port map (
      D => \U1.RSR\(6),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(6));
  \II_u1_rbrio[7]\: OFS1P3DX port map (
      D => \U1.RSR\(7),
      SP => \U1.PARITY8\,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => \U1.RBR\(7));
  II_u1_framing_errorio: OFS1P3DX port map (
      D => N_25_A2,
      SP => UN1_PARITY7_2,
      SCLK => \U1.CLKDIV\(3),
      CD => GND,
      Q => FRAMING_ERROR_C);
  II_GSR_INST: GSR port map (
      GSR => GSRN);
  II_GSRN: INV port map (
      A => RST_C,
      Z => GSRN);
  II_sdo_pad: OB port map (
      I => SDO_C,
      O => sdo);
  II_wrn_pad: IB port map (
      I => wrn,
      O => WRN_C);
  II_tsre_pad: OB port map (
      I => TSRE_C,
      O => tsre);
  II_tbre_pad: OB port map (
      I => TBRE_C,
      O => tbre);
  \II_din_pad[7]\: IB port map (
      I => din(7),
      O => DIN_C(7));
  \II_din_pad[6]\: IB port map (
      I => din(6),
      O => DIN_C(6));
  \II_din_pad[5]\: IB port map (
      I => din(5),
      O => DIN_C(5));
  \II_din_pad[4]\: IB port map (
      I => din(4),
      O => DIN_C(4));
  \II_din_pad[3]\: IB port map (
      I => din(3),
      O => DIN_C(3));
  \II_din_pad[2]\: IB port map (
      I => din(2),
      O => DIN_C(2));
  \II_din_pad[1]\: IB port map (
      I => din(1),
      O => DIN_C(1));
  \II_din_pad[0]\: IB port map (
      I => din(0),
      O => DIN_C(0));
  II_rdn_pad: IB port map (
      I => rdn,
      O => RDN_C);
  II_rst_pad: IB port map (
      I => rst,
      O => RST_C);
  II_clk16x_pad: IB port map (
      I => clk16x,
      O => CLK16X_C);
  II_rxd_pad: IB port map (
      I => rxd,
      O => RXD_C);
  II_parity_error_pad: OB port map (
      I => PARITY_ERROR_C,
      O => parity_error);
  II_framing_error_pad: OB port map (
      I => FRAMING_ERROR_C,
      O => framing_error);
  II_data_ready_pad: OB port map (
      I => DATA_READY_C,
      O => data_ready);
  \II_dout_pad[7]\: OBZ port map (
      I => \U1.RBR\(7),
      T => RDN_C,
      O => dout(7));
  \II_dout_pad[6]\: OBZ port map (
      I => \U1.RBR\(6),
      T => RDN_C,
      O => dout(6));
  \II_dout_pad[5]\: OBZ port map (
      I => \U1.RBR\(5),
      T => RDN_C,
      O => dout(5));
  \II_dout_pad[4]\: OBZ port map (
      I => \U1.RBR\(4),
      T => RDN_C,
      O => dout(4));
  \II_dout_pad[3]\: OBZ port map (
      I => \U1.RBR\(3),
      T => RDN_C,
      O => dout(3));
  \II_dout_pad[2]\: OBZ port map (
      I => \U1.RBR\(2),
      T => RDN_C,
      O => dout(2));
  \II_dout_pad[1]\: OBZ port map (
      I => \U1.RBR\(1),
      T => RDN_C,
      O => dout(1));
  \II_dout_pad[0]\: OBZ port map (
      I => \U1.RBR\(0),
      T => RDN_C,
      O => dout(0));
  \U2.UN1_NO_BITS_SENT_3_P4\ <= (not \U2.NO_BITS_SENT_FAST\(1) and not \U2.NO_BITS_SENT_FAST\(2) and not \U2.NO_BITS_SENT_FAST\(3)) or 
	  (not \U2.NO_BITS_SENT_FAST\(0) and not \U2.NO_BITS_SENT_FAST\(2) and not \U2.NO_BITS_SENT_FAST\(3));
  G0_2 <= (not \U2.NO_BITS_SENT\(1)) or 
	  (\U2.NO_BITS_SENT\(0) and not \U2.NO_BITS_SENT\(3)) or 
	  (\U2.NO_BITS_SENT\(2)) or 
	  (not \U2.NO_BITS_SENT\(0) and \U2.NO_BITS_SENT\(3));
  \U2.UN3_P4\ <= (\U2.NO_BITS_SENT_2_REP1\ and \U2.NO_BITS_SENT_FAST\(3)) or 
	  (\U2.NO_BITS_SENT_0_REP1\ and \U2.NO_BITS_SENT_FAST\(1) and \U2.NO_BITS_SENT_FAST\(3));
  \U2.N_23_I\ <= (not \U2.UN1_NO_BITS_SENT_3_P4\ and not \U2.UN3_P4\) or 
	  (not G0_2) or 
	  (\U2.PARITY11\);
  \U2.PARITY11\ <= \U2.NO_BITS_SENT\(3) and not \U2.NO_BITS_SENT_0_REP1\ and \U2.NO_BITS_SENT_2_REP1\ and not \U2.NO_BITS_SENT_FAST\(1);
  \U2.PARITY9\ <= (\U2.NO_BITS_SENT\(3) and not \U2.NO_BITS_SENT_0_REP1\ and not \U2.NO_BITS_SENT_2_REP1\) or 
	  (\U2.NO_BITS_SENT\(1) and not \U2.NO_BITS_SENT\(3) and \U2.NO_BITS_SENT_0_REP1\) or 
	  (not \U2.NO_BITS_SENT\(1) and \U2.NO_BITS_SENT\(3) and not \U2.NO_BITS_SENT_2_REP1\) or 
	  (not \U2.NO_BITS_SENT\(3) and \U2.NO_BITS_SENT_2_REP1\);
  \U2.N_22_I\ <= (G0_7) or 
	  (\U2.PARITY11\) or 
	  (\U2.PARITY9\ and \U2.TSR\(7));
  \U1.PARITY7\ <= (\U1.NO_BITS_RCVD\(0) and not \U1.NO_BITS_RCVD\(3)) or 
	  (\U1.NO_BITS_RCVD\(1) and not \U1.NO_BITS_RCVD\(3)) or 
	  (\U1.NO_BITS_RCVD\(2) and not \U1.NO_BITS_RCVD\(3)) or 
	  (not \U1.NO_BITS_RCVD\(1) and not \U1.NO_BITS_RCVD\(2) and \U1.NO_BITS_RCVD\(3));
  G0_7_X0 <= \U2.NO_BITS_SENT\(1) and \U2.NO_BITS_SENT_0_REP1\ and \U2.NO_BITS_SENT_FAST\(3) and \U2.PARITY\;
  G0_7 <= G0_7_X0 and not \U2.NO_BITS_SENT\(2);
  II_u1: rcvr port map (
      rsr(0) => \U1.RSR\(0),
      rsr(1) => \U1.RSR\(1),
      rsr(2) => \U1.RSR\(2),
      rsr(3) => \U1.RSR\(3),
      rsr(4) => \U1.RSR\(4),
      rsr(5) => \U1.RSR\(5),
      rsr(6) => \U1.RSR\(6),
      rsr(7) => \U1.RSR\(7),
      clkdiv_3 => \U1.CLKDIV\(3),
      no_bits_rcvd(0) => \U1.NO_BITS_RCVD\(0),
      no_bits_rcvd(1) => \U1.NO_BITS_RCVD\(1),
      no_bits_rcvd(2) => \U1.NO_BITS_RCVD\(2),
      no_bits_rcvd(3) => \U1.NO_BITS_RCVD\(3),
      un1_parity7_2 => UN1_PARITY7_2,
      N_25_a2 => N_25_A2,
      rst_c => RST_C,
      rdn_c => RDN_C,
      VCC => VCC,
      GSRN => GSRN,
      clk16x_c => CLK16X_C,
      rxd1 => \U1.RXD1\,
      GND => GND,
      data_ready_c => DATA_READY_C,
      parity7 => \U1.PARITY7\,
      parity8 => \U1.PARITY8\,
      parity_error_c => PARITY_ERROR_C);
  II_u2: txmit port map (
      tbr(0) => \U2.TBR\(0),
      tbr(1) => \U2.TBR\(1),
      tbr(2) => \U2.TBR\(2),
      tbr(3) => \U2.TBR\(3),
      tbr(4) => \U2.TBR\(4),
      tbr(5) => \U2.TBR\(5),
      tbr(6) => \U2.TBR\(6),
      tbr(7) => \U2.TBR\(7),
      tsr_7 => \U2.TSR\(7),
      no_bits_sent_fast(0) => \U2.NO_BITS_SENT_FAST\(0),
      no_bits_sent_fast(1) => \U2.NO_BITS_SENT_FAST\(1),
      no_bits_sent_fast(2) => \U2.NO_BITS_SENT_FAST\(2),
      no_bits_sent_fast(3) => \U2.NO_BITS_SENT_FAST\(3),
      no_bits_sent(0) => \U2.NO_BITS_SENT\(0),
      no_bits_sent(1) => \U2.NO_BITS_SENT\(1),
      no_bits_sent(2) => \U2.NO_BITS_SENT\(2),
      no_bits_sent(3) => \U2.NO_BITS_SENT\(3),
      clkdiv_i_0(3) => \U2.CLKDIV_I_0\(3),
      un1_clk1x_enable10_2_i => \U2.UN1_CLK1X_ENABLE10_2_I\,
      N_26_i => \U2.N_26_I\,
      rst_c => RST_C,
      VCC => VCC,
      parity => \U2.PARITY\,
      parity9 => \U2.PARITY9\,
      wrn_c => WRN_C,
      GSRN => GSRN,
      clk16x_c => CLK16X_C,
      N_21_i => \U2.N_21_I\,
      GND => GND,
      no_bits_sent_2_rep1 => \U2.NO_BITS_SENT_2_REP1\,
      no_bits_sent_0_rep1 => \U2.NO_BITS_SENT_0_REP1\);
  NN_1 <= '0';
  NN_2 <= '1';
end beh;