uart.vhm

UART 串口程序

  no_bits_sent(3) <= NO_BITS_SENT_3_INT_33;
  clkdiv_i_0(3) <= CLKDIV_I_0_3_INT_34;
  parity <= PARITY_INT_35;
  no_bits_sent_2_rep1 <= NO_BITS_SENT_2_REP1_INT_36;
  no_bits_sent_0_rep1 <= NO_BITS_SENT_0_REP1_INT_37;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp;
use xp.components.all;

entity rcvr is
port(
  rsr : out std_logic_vector (7 downto 0);
  clkdiv_3 :  out std_logic;
  no_bits_rcvd : out std_logic_vector (3 downto 0);
  un1_parity7_2 :  out std_logic;
  N_25_a2 :  out std_logic;
  rst_c :  in std_logic;
  rdn_c :  in std_logic;
  VCC :  in std_logic;
  GSRN :  in std_logic;
  clk16x_c :  in std_logic;
  rxd1 :  in std_logic;
  GND :  in std_logic;
  data_ready_c :  out std_logic;
  parity7 :  in std_logic;
  parity8 :  out std_logic;
  parity_error_c :  out std_logic);
end rcvr;

architecture beh of rcvr is
  signal RSR_QN : std_logic_vector (7 downto 0);
  signal NO_BITS_RCVD_I : std_logic_vector (0 to 0);
  signal NO_BITS_RCVD_QN : std_logic_vector (3 downto 0);
  signal CLKDIV_QN_0 : std_logic_vector (3 downto 0);
  signal CLKDIV_4 : std_logic_vector (3 downto 0);
  signal CLKDIV : std_logic_vector (2 downto 0);
  signal CLKDIV_I : std_logic_vector (3 to 3);
  signal RXD2_QN : std_logic ;
  signal RSR_0_INT_9 : std_logic ;
  signal RSR_1_INT_10 : std_logic ;
  signal RSR_2_INT_11 : std_logic ;
  signal RSR_3_INT_12 : std_logic ;
  signal RSR_4_INT_13 : std_logic ;
  signal RSR_5_INT_14 : std_logic ;
  signal RSR_6_INT_15 : std_logic ;
  signal FB : std_logic ;
  signal PARITY_ERROR_C_INT_24 : std_logic ;
  signal PARITY_ERROR_QN : std_logic ;
  signal PARITY_QN_0 : std_logic ;
  signal FB_0 : std_logic ;
  signal DATA_READY_C_INT_22 : std_logic ;
  signal DATA_READY_QN : std_logic ;
  signal CLK1X_ENABLE_QN_0 : std_logic ;
  signal RSR_7_INT_16 : std_logic ;
  signal PARITY_3 : std_logic ;
  signal NO_BITS_RCVD_N1 : std_logic ;
  signal CLKDIV_4_P4 : std_logic ;
  signal N_30_I : std_logic ;
  signal N_31_I : std_logic ;
  signal NO_BITS_RCVD_N2 : std_logic ;
  signal DATA_READY9 : std_logic ;
  signal RXD2 : std_logic ;
  signal NO_BITS_RCVD_1_INT_19 : std_logic ;
  signal NO_BITS_RCVD_2_INT_20 : std_logic ;
  signal NO_BITS_RCVD_N3 : std_logic ;
  signal CLK1X_ENABLE : std_logic ;
  signal PARITY : std_logic ;
  signal PARITY8_INT_23 : std_logic ;
  signal CLK1X_ENABLE10 : std_logic ;
  signal NO_BITS_RCVD_0_INT_18 : std_logic ;
  signal NO_BITS_RCVD_3_INT_21 : std_logic ;
  signal UN1_NO_BITS_RCVD_1_0 : std_logic ;
  signal N_29_I : std_logic ;
  signal CLKDIV_3_INT_17 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  \II_no_bits_rcvd_i[0]\: INV port map (
      A => NO_BITS_RCVD_0_INT_18,
      Z => NO_BITS_RCVD_I(0));
  FB <= (not PARITY8_INT_23 and not parity7 and not PARITY) or 
	  (PARITY_ERROR_C_INT_24);
  FB_0 <= (DATA_READY_C_INT_22) or 
	  (DATA_READY9);
  II_rxd2: FD1S3AY port map (
      D => rxd1,
      CK => clk16x_c,
      Q => RXD2);
  \II_rsr[0]\: FD1P3AX port map (
      D => RXD2,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_0_INT_9);
  \II_rsr[1]\: FD1P3AX port map (
      D => RSR_0_INT_9,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_1_INT_10);
  \II_rsr[2]\: FD1P3AX port map (
      D => RSR_1_INT_10,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_2_INT_11);
  \II_rsr[3]\: FD1P3AX port map (
      D => RSR_2_INT_11,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_3_INT_12);
  \II_rsr[4]\: FD1P3AX port map (
      D => RSR_3_INT_12,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_4_INT_13);
  \II_rsr[5]\: FD1P3AX port map (
      D => RSR_4_INT_13,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_5_INT_14);
  \II_rsr[6]\: FD1P3AX port map (
      D => RSR_5_INT_14,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_6_INT_15);
  \II_rsr[7]\: FD1P3AX port map (
      D => RSR_6_INT_15,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => RSR_7_INT_16);
  II_parity_error: FD1S3AX port map (
      D => FB,
      CK => CLKDIV_3_INT_17,
      Q => PARITY_ERROR_C_INT_24);
  II_parity: FD1P3AY port map (
      D => PARITY_3,
      SP => parity7,
      CK => CLKDIV_3_INT_17,
      Q => PARITY);
  \II_no_bits_rcvd[0]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_RCVD_I(0),
    CK => CLKDIV_3_INT_17,
    CD => N_31_I,
    Q => NO_BITS_RCVD_0_INT_18);
  \II_no_bits_rcvd[1]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_RCVD_N1,
    CK => CLKDIV_3_INT_17,
    CD => N_31_I,
    Q => NO_BITS_RCVD_1_INT_19);
  \II_no_bits_rcvd[2]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_RCVD_N2,
    CK => CLKDIV_3_INT_17,
    CD => N_31_I,
    Q => NO_BITS_RCVD_2_INT_20);
  \II_no_bits_rcvd[3]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_RCVD_N3,
    CK => CLKDIV_3_INT_17,
    CD => N_31_I,
    Q => NO_BITS_RCVD_3_INT_21);
  II_data_ready: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => FB_0,
    CK => clk16x_c,
    CD => N_30_I,
    Q => DATA_READY_C_INT_22);
  \II_clkdiv[0]\: FD1S3AX port map (
      D => CLKDIV_4(0),
      CK => clk16x_c,
      Q => CLKDIV(0));
  \II_clkdiv[1]\: FD1S3AX port map (
      D => CLKDIV_4(1),
      CK => clk16x_c,
      Q => CLKDIV(1));
  \II_clkdiv[2]\: FD1S3AX port map (
      D => CLKDIV_4(2),
      CK => clk16x_c,
      Q => CLKDIV(2));
  \II_clkdiv[3]\: FD1S3AX port map (
      D => CLKDIV_4(3),
      CK => clk16x_c,
      Q => CLKDIV_I(3));
  II_clk1x_enable: FD1P3AX port map (
      D => CLK1X_ENABLE10,
      SP => N_29_I,
      CK => clk16x_c,
      Q => CLK1X_ENABLE);
  CLKDIV_4_P4 <= CLK1X_ENABLE and CLKDIV(0) and CLKDIV(1) and CLKDIV(2);
  PARITY_3 <= (PARITY and not RSR_7_INT_16) or 
	  (not PARITY and RSR_7_INT_16);
  CLK1X_ENABLE10 <= not rxd1 and RXD2;
  NO_BITS_RCVD_N1 <= (NO_BITS_RCVD_0_INT_18 and not NO_BITS_RCVD_1_INT_19) or 
	  (not NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_1_INT_19);
  CLKDIV_4(0) <= (CLK1X_ENABLE and not CLKDIV(0)) or 
	  (not CLK1X_ENABLE and CLKDIV(0));
  CLKDIV_4(3) <= (CLKDIV_3_INT_17 and not CLKDIV_4_P4) or 
	  (not CLKDIV_3_INT_17 and CLKDIV_4_P4);
  UN1_NO_BITS_RCVD_1_0 <= not NO_BITS_RCVD_1_INT_19 and NO_BITS_RCVD_2_INT_20;
  N_30_I <= (not rdn_c) or 
	  (rst_c);
  N_31_I <= (not CLK1X_ENABLE) or 
	  (rst_c);
  NO_BITS_RCVD_N2 <= (NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_1_INT_19 and not NO_BITS_RCVD_2_INT_20) or 
	  (not NO_BITS_RCVD_1_INT_19 and NO_BITS_RCVD_2_INT_20) or 
	  (not NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_2_INT_20);
  CLKDIV_4(1) <= (CLK1X_ENABLE and CLKDIV(0) and not CLKDIV(1)) or 
	  (not CLKDIV(0) and CLKDIV(1)) or 
	  (not CLK1X_ENABLE and CLKDIV(1));
  PARITY8_INT_23 <= not NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_1_INT_19 and not NO_BITS_RCVD_2_INT_20 and NO_BITS_RCVD_3_INT_21;
  DATA_READY9 <= NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_1_INT_19 and not NO_BITS_RCVD_2_INT_20 and NO_BITS_RCVD_3_INT_21;
  N_25_a2 <= NO_BITS_RCVD_1_INT_19 and not NO_BITS_RCVD_2_INT_20 and NO_BITS_RCVD_3_INT_21 and not RXD2;
  NO_BITS_RCVD_N3 <= (NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_1_INT_19 and NO_BITS_RCVD_2_INT_20 and not NO_BITS_RCVD_3_INT_21) or 
	  (not NO_BITS_RCVD_2_INT_20 and NO_BITS_RCVD_3_INT_21) or 
	  (not NO_BITS_RCVD_1_INT_19 and NO_BITS_RCVD_3_INT_21) or 
	  (not NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_3_INT_21);
  CLKDIV_4(2) <= (CLK1X_ENABLE and CLKDIV(0) and CLKDIV(1) and not CLKDIV(2)) or 
	  (not CLKDIV(1) and CLKDIV(2)) or 
	  (not CLKDIV(0) and CLKDIV(2)) or 
	  (not CLK1X_ENABLE and CLKDIV(2));
  un1_parity7_2 <= PARITY and not parity7 and not PARITY8_INT_23;
  N_29_I <= (CLK1X_ENABLE10) or 
	  (not NO_BITS_RCVD_0_INT_18 and NO_BITS_RCVD_3_INT_21 and UN1_NO_BITS_RCVD_1_0);
  CLKDIV_3_INT_17 <= CLKDIV_I(3);
  NN_1 <= '0';
  NN_2 <= '1';
  rsr(0) <= RSR_0_INT_9;
  rsr(1) <= RSR_1_INT_10;
  rsr(2) <= RSR_2_INT_11;
  rsr(3) <= RSR_3_INT_12;
  rsr(4) <= RSR_4_INT_13;
  rsr(5) <= RSR_5_INT_14;
  rsr(6) <= RSR_6_INT_15;
  rsr(7) <= RSR_7_INT_16;
  clkdiv_3 <= CLKDIV_3_INT_17;
  no_bits_rcvd(0) <= NO_BITS_RCVD_0_INT_18;
  no_bits_rcvd(1) <= NO_BITS_RCVD_1_INT_19;
  no_bits_rcvd(2) <= NO_BITS_RCVD_2_INT_20;
  no_bits_rcvd(3) <= NO_BITS_RCVD_3_INT_21;
  data_ready_c <= DATA_READY_C_INT_22;
  parity8 <= PARITY8_INT_23;
  parity_error_c <= PARITY_ERROR_C_INT_24;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp;
use xp.components.all;

entity uart is
port(
  dout : out std_logic_vector (7 downto 0);
  data_ready :  out std_logic;
  framing_error :  out std_logic;
  parity_error :  out std_logic;
  rxd :  in std_logic;
  clk16x :  in std_logic;
  rst :  in std_logic;
  rdn :  in std_logic;
  din : in std_logic_vector (7 downto 0);
  tbre :  out std_logic;
  tsre :  out std_logic;
  wrn :  in std_logic;
  sdo :  out std_logic);
end uart;

architecture beh of uart is
  signal \U2.NO_BITS_SENT\ : std_logic_vector (3 downto 0);
  signal \U2.TBR\ : std_logic_vector (7 downto 0);
  signal \U2.TSR\ : std_logic_vector (7 to 7);
  signal \U1.NO_BITS_RCVD\ : std_logic_vector (3 downto 0);
  signal \U1.RSR\ : std_logic_vector (7 downto 0);
  signal \U1.RBR\ : std_logic_vector (7 downto 0);
  signal \U1.CLKDIV\ : std_logic_vector (3 to 3);
  signal \U2.NO_BITS_SENT_FAST\ : std_logic_vector (3 downto 0);
  signal DIN_C : std_logic_vector (7 downto 0);
  signal \U2.CLKDIV_I_0\ : std_logic_vector (3 to 3);
  signal \U2.PARITY\ : std_logic ;
  signal \U2.PARITY9\ : std_logic ;
  signal \U1.RXD1\ : std_logic ;
  signal \U1.PARITY8\ : std_logic ;
  signal N_25_A2 : std_logic ;
  signal UN1_PARITY7_2 : std_logic ;
  signal \U1.PARITY7\ : std_logic ;
  signal \U2.PARITY11\ : std_logic ;
  signal \U2.UN1_NO_BITS_SENT_3_P4\ : std_logic ;
  signal \U2.UN3_P4\ : std_logic ;
  signal \U2.UN1_CLK1X_ENABLE10_2_I\ : std_logic ;
  signal \U2.N_26_I\ : std_logic ;
  signal \U2.N_21_I\ : std_logic ;
  signal \U2.N_22_I\ : std_logic ;
  signal \U2.N_23_I\ : std_logic ;
  signal G0_2 : std_logic ;
  signal G0_7 : std_logic ;
  signal \U2.NO_BITS_SENT_0_REP1\ : std_logic ;
  signal \U2.NO_BITS_SENT_2_REP1\ : std_logic ;
  signal G0_7_X0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal DATA_READY_C : std_logic ;
  signal FRAMING_ERROR_C : std_logic ;
  signal PARITY_ERROR_C : std_logic ;
  signal RXD_C : std_logic ;
  signal CLK16X_C : std_logic ;
  signal RST_C : std_logic ;
  signal RDN_C : std_logic ;
  signal TBRE_C : std_logic ;
  signal TSRE_C : std_logic ;
  signal WRN_C : std_logic ;
  signal SDO_C : std_logic ;
  signal GSRN : std_logic ;
  signal WRN_C_I : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component rcvr
    port(
      rsr : out std_logic_vector(7 downto 0);
      clkdiv_3 : out std_logic;
      no_bits_rcvd : out std_logic_vector(3 downto 0);
      un1_parity7_2 : out std_logic;
      N_25_a2 : out std_logic;
      rst_c : in std_logic;
      rdn_c : in std_logic;
      VCC : in std_logic;