uart.vhm

UART 串口程序

--
-- Written by Synplicity
-- Tue Jul 17 10:47:47 2007
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp;
use xp.components.all;

entity txmit is
port(
  tbr : in std_logic_vector (7 downto 0);
  tsr_7 :  out std_logic;
  no_bits_sent_fast : out std_logic_vector (3 downto 0);
  no_bits_sent : out std_logic_vector (3 downto 0);
  clkdiv_i_0 : out std_logic_vector (3 downto 3);
  un1_clk1x_enable10_2_i :  out std_logic;
  N_26_i :  out std_logic;
  rst_c :  in std_logic;
  VCC :  in std_logic;
  parity :  out std_logic;
  parity9 :  in std_logic;
  wrn_c :  in std_logic;
  GSRN :  in std_logic;
  clk16x_c :  in std_logic;
  N_21_i :  out std_logic;
  GND :  in std_logic;
  no_bits_sent_2_rep1 :  out std_logic;
  no_bits_sent_0_rep1 :  out std_logic);
end txmit;

architecture beh of txmit is
  signal TSR_QN : std_logic_vector (7 downto 0);
  signal NO_BITS_SENT_I : std_logic_vector (0 to 0);
  signal NO_BITS_SENT_QN : std_logic_vector (3 downto 0);
  signal NO_BITS_SENT_FAST_I : std_logic_vector (0 to 0);
  signal NO_BITS_SENT_FAST_QN : std_logic_vector (3 downto 0);
  signal CLKDIV_QN : std_logic_vector (3 downto 0);
  signal CLKDIV_4 : std_logic_vector (3 downto 0);
  signal TSR_6 : std_logic_vector (7 downto 0);
  signal CLKDIV : std_logic_vector (3 downto 0);
  signal TSR : std_logic_vector (6 downto 0);
  signal CLKDIV_I : std_logic_vector (3 to 3);
  signal WRN2_QN : std_logic ;
  signal WRN1_QN : std_logic ;
  signal CLKDIV_I_0_3_INT_34 : std_logic ;
  signal PARITY_QN : std_logic ;
  signal NO_BITS_SENT_N2_REP1 : std_logic ;
  signal NO_BITS_SENT_2_REP1_QN : std_logic ;
  signal NO_BITS_SENT_0_REP1_I : std_logic ;
  signal NO_BITS_SENT_0_REP1_QN : std_logic ;
  signal NO_BITS_SENT_N2_FAST : std_logic ;
  signal NO_BITS_SENT_N2 : std_logic ;
  signal NO_BITS_SENT_N3_FAST : std_logic ;
  signal NO_BITS_SENT_N3 : std_logic ;
  signal UN1_CLK1X_ENABLE11 : std_logic ;
  signal CLK1X_ENABLE_QN : std_logic ;
  signal NO_BITS_SENT_N1 : std_logic ;
  signal CLK1X_ENABLE10 : std_logic ;
  signal PARITY_INT_35 : std_logic ;
  signal TSR_7_INT_25 : std_logic ;
  signal PARITY_3 : std_logic ;
  signal CLKDIV_4_P4 : std_logic ;
  signal N_27_I : std_logic ;
  signal CLK1X_ENABLE : std_logic ;
  signal PARITY7 : std_logic ;
  signal NO_BITS_SENT_1_INT_31 : std_logic ;
  signal NO_BITS_SENT_2_INT_32 : std_logic ;
  signal NO_BITS_SENT_3_INT_33 : std_logic ;
  signal NO_BITS_SENT_0_INT_30 : std_logic ;
  signal NO_BITS_SENT_N1_FAST : std_logic ;
  signal NO_BITS_SENT_FAST_0_INT_26 : std_logic ;
  signal NO_BITS_SENT_FAST_2_INT_28 : std_logic ;
  signal NO_BITS_SENT_FAST_3_INT_29 : std_logic ;
  signal N_24_I : std_logic ;
  signal NO_BITS_SENT_0_REP1_INT_37 : std_logic ;
  signal NO_BITS_SENT_2_REP1_INT_36 : std_logic ;
  signal NO_BITS_SENT_FAST_1_INT_27 : std_logic ;
  signal N_24_I_L1 : std_logic ;
  signal UN1_CLK1X_ENABLE10_2_0 : std_logic ;
  signal WRN2 : std_logic ;
  signal WRN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  \II_clkdiv_i[3]\: INV port map (
      A => CLKDIV(3),
      Z => CLKDIV_I_0_3_INT_34);
  \II_no_bits_sent_i[0]\: INV port map (
      A => NO_BITS_SENT_0_INT_30,
      Z => NO_BITS_SENT_I(0));
  \II_no_bits_sent_fast_i[0]\: INV port map (
      A => NO_BITS_SENT_FAST_0_INT_26,
      Z => NO_BITS_SENT_FAST_I(0));
  II_no_bits_sent_0_rep1_i: INV port map (
      A => NO_BITS_SENT_0_REP1_INT_37,
      Z => NO_BITS_SENT_0_REP1_I);
  NO_BITS_SENT_N3_FAST <= (NO_BITS_SENT_FAST_3_INT_29 and not NO_BITS_SENT_0_INT_30) or 
	  (NO_BITS_SENT_FAST_3_INT_29 and not NO_BITS_SENT_1_INT_31) or 
	  (NO_BITS_SENT_FAST_3_INT_29 and not NO_BITS_SENT_2_INT_32) or 
	  (not NO_BITS_SENT_FAST_3_INT_29 and NO_BITS_SENT_2_INT_32 and NO_BITS_SENT_1_INT_31 and NO_BITS_SENT_0_INT_30);
  NO_BITS_SENT_N2_REP1 <= (NO_BITS_SENT_2_REP1_INT_36 and not NO_BITS_SENT_0_INT_30) or 
	  (NO_BITS_SENT_2_REP1_INT_36 and not NO_BITS_SENT_1_INT_31) or 
	  (not NO_BITS_SENT_2_REP1_INT_36 and NO_BITS_SENT_1_INT_31 and NO_BITS_SENT_0_INT_30);
  NO_BITS_SENT_N2_FAST <= (NO_BITS_SENT_FAST_2_INT_28 and not NO_BITS_SENT_0_INT_30) or 
	  (NO_BITS_SENT_FAST_2_INT_28 and not NO_BITS_SENT_1_INT_31) or 
	  (not NO_BITS_SENT_FAST_2_INT_28 and NO_BITS_SENT_1_INT_31 and NO_BITS_SENT_0_INT_30);
  UN1_CLK1X_ENABLE11 <= (not UN1_CLK1X_ENABLE10_2_0 and NO_BITS_SENT_0_INT_30) or 
	  (WRN2 and not WRN1);
  NO_BITS_SENT_N3 <= (NO_BITS_SENT_3_INT_33 and not NO_BITS_SENT_0_INT_30) or 
	  (NO_BITS_SENT_3_INT_33 and not NO_BITS_SENT_1_INT_31) or 
	  (NO_BITS_SENT_3_INT_33 and not NO_BITS_SENT_2_INT_32) or 
	  (not NO_BITS_SENT_3_INT_33 and NO_BITS_SENT_2_INT_32 and NO_BITS_SENT_1_INT_31 and NO_BITS_SENT_0_INT_30);
  N_21_i <= (not NO_BITS_SENT_3_INT_33) or 
	  (WRN2 and not WRN1);
  NO_BITS_SENT_N2 <= (NO_BITS_SENT_2_INT_32 and not NO_BITS_SENT_0_INT_30) or 
	  (NO_BITS_SENT_2_INT_32 and not NO_BITS_SENT_1_INT_31) or 
	  (not NO_BITS_SENT_2_INT_32 and NO_BITS_SENT_1_INT_31 and NO_BITS_SENT_0_INT_30);
  II_wrn2: FD1S3AY port map (
      D => WRN1,
      CK => clk16x_c,
      Q => WRN2);
  II_wrn1: FD1S3AY port map (
      D => wrn_c,
      CK => clk16x_c,
      Q => WRN1);
  \II_tsr[0]\: FD1P3AX port map (
      D => TSR_6(0),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR(0));
  \II_tsr[1]\: FD1P3AX port map (
      D => TSR_6(1),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR(1));
  \II_tsr[2]\: FD1P3AX port map (
      D => TSR_6(2),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR(2));
  \II_tsr[3]\: FD1P3AX port map (
      D => TSR_6(3),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR(3));
  \II_tsr[4]\: FD1P3AX port map (
      D => TSR_6(4),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR(4));
  \II_tsr[5]\: FD1P3AX port map (
      D => TSR_6(5),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR(5));
  \II_tsr[6]\: FD1P3AX port map (
      D => TSR_6(6),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR(6));
  \II_tsr[7]\: FD1P3AX port map (
      D => TSR_6(7),
      SP => N_24_I,
      CK => CLKDIV_I_0_3_INT_34,
      Q => TSR_7_INT_25);
  II_parity: FD1P3AY port map (
      D => PARITY_3,
      SP => parity9,
      CK => CLKDIV_I_0_3_INT_34,
      Q => PARITY_INT_35);
  \II_no_bits_sent[0]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_I(0),
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_0_INT_30);
  \II_no_bits_sent_fast[0]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_FAST_I(0),
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_FAST_0_INT_26);
  \II_no_bits_sent_fast[1]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_N1_FAST,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_FAST_1_INT_27);
  II_no_bits_sent_2_rep1: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_N2_REP1,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_2_REP1_INT_36);
  II_no_bits_sent_0_rep1: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_0_REP1_I,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_0_REP1_INT_37);
  \II_no_bits_sent[1]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_N1,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_1_INT_31);
  \II_no_bits_sent_fast[2]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_N2_FAST,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_FAST_2_INT_28);
  \II_no_bits_sent[2]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_N2,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_2_INT_32);
  \II_no_bits_sent_fast[3]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_N3_FAST,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_FAST_3_INT_29);
  \II_no_bits_sent[3]\: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => NO_BITS_SENT_N3,
    CK => CLKDIV(3),
    CD => N_27_I,
    Q => NO_BITS_SENT_3_INT_33);
  \II_clkdiv[0]\: FD1S3AX port map (
      D => CLKDIV_4(0),
      CK => clk16x_c,
      Q => CLKDIV(0));
  \II_clkdiv[1]\: FD1S3AX port map (
      D => CLKDIV_4(1),
      CK => clk16x_c,
      Q => CLKDIV(1));
  \II_clkdiv[2]\: FD1S3AX port map (
      D => CLKDIV_4(2),
      CK => clk16x_c,
      Q => CLKDIV(2));
  \II_clkdiv[3]\: FD1S3AX port map (
      D => CLKDIV_4(3),
      CK => clk16x_c,
      Q => CLKDIV_I(3));
  II_clk1x_enable: FD1P3AX port map (
      D => CLK1X_ENABLE10,
      SP => UN1_CLK1X_ENABLE11,
      CK => clk16x_c,
      Q => CLK1X_ENABLE);
  CLKDIV_4_P4 <= CLK1X_ENABLE and CLKDIV(0) and CLKDIV(1) and CLKDIV(2);
  NO_BITS_SENT_N1 <= (NO_BITS_SENT_0_INT_30 and not NO_BITS_SENT_1_INT_31) or 
	  (not NO_BITS_SENT_0_INT_30 and NO_BITS_SENT_1_INT_31);
  CLK1X_ENABLE10 <= not WRN1 and WRN2;
  PARITY_3 <= (PARITY_INT_35 and not TSR_7_INT_25) or 
	  (not PARITY_INT_35 and TSR_7_INT_25);
  CLKDIV_4(0) <= (CLK1X_ENABLE and not CLKDIV(0)) or 
	  (not CLK1X_ENABLE and CLKDIV(0));
  CLKDIV_4(3) <= (CLKDIV(3) and not CLKDIV_4_P4) or 
	  (not CLKDIV(3) and CLKDIV_4_P4);
  N_27_I <= (not CLK1X_ENABLE) or 
	  (rst_c);
  CLKDIV_4(1) <= (CLK1X_ENABLE and CLKDIV(0) and not CLKDIV(1)) or 
	  (not CLKDIV(0) and CLKDIV(1)) or 
	  (not CLK1X_ENABLE and CLKDIV(1));
  PARITY7 <= NO_BITS_SENT_FAST_0_INT_26 and not NO_BITS_SENT_FAST_1_INT_27 and not NO_BITS_SENT_FAST_2_INT_28 and not NO_BITS_SENT_FAST_3_INT_29;
  TSR_6(0) <= PARITY7 and tbr(0);
  CLKDIV_4(2) <= (CLK1X_ENABLE and CLKDIV(0) and CLKDIV(1) and not CLKDIV(2)) or 
	  (not CLKDIV(1) and CLKDIV(2)) or 
	  (not CLKDIV(0) and CLKDIV(2)) or 
	  (not CLK1X_ENABLE and CLKDIV(2));
  UN1_CLK1X_ENABLE10_2_0 <= (not NO_BITS_SENT_1_INT_31 and not NO_BITS_SENT_3_INT_33) or 
	  (NO_BITS_SENT_0_INT_30 and not NO_BITS_SENT_3_INT_33) or 
	  (NO_BITS_SENT_2_INT_32 and not NO_BITS_SENT_3_INT_33) or 
	  (not NO_BITS_SENT_2_INT_32 and NO_BITS_SENT_3_INT_33) or 
	  (not NO_BITS_SENT_0_INT_30 and NO_BITS_SENT_3_INT_33) or 
	  (NO_BITS_SENT_1_INT_31 and NO_BITS_SENT_3_INT_33);
  TSR_6(1) <= (PARITY7 and tbr(1)) or 
	  (not PARITY7 and TSR(0));
  TSR_6(2) <= (PARITY7 and tbr(2)) or 
	  (not PARITY7 and TSR(1));
  TSR_6(3) <= (PARITY7 and tbr(3)) or 
	  (not PARITY7 and TSR(2));
  TSR_6(4) <= (PARITY7 and tbr(4)) or 
	  (not PARITY7 and TSR(3));
  TSR_6(5) <= (PARITY7 and tbr(5)) or 
	  (not PARITY7 and TSR(4));
  TSR_6(6) <= (PARITY7 and tbr(6)) or 
	  (not PARITY7 and TSR(5));
  TSR_6(7) <= (PARITY7 and tbr(7)) or 
	  (not PARITY7 and TSR(6));
  N_26_i <= (NO_BITS_SENT_0_INT_30 and not NO_BITS_SENT_1_INT_31 and not NO_BITS_SENT_2_INT_32 and not NO_BITS_SENT_3_INT_33) or 
	  (not NO_BITS_SENT_0_INT_30 and not NO_BITS_SENT_1_INT_31 and NO_BITS_SENT_2_INT_32 and NO_BITS_SENT_3_INT_33);
  NO_BITS_SENT_N1_FAST <= (NO_BITS_SENT_0_INT_30 and not NO_BITS_SENT_FAST_1_INT_27) or 
	  (not NO_BITS_SENT_0_INT_30 and NO_BITS_SENT_FAST_1_INT_27);
  N_24_I <= (NO_BITS_SENT_FAST_0_INT_26 and not NO_BITS_SENT_FAST_3_INT_29) or 
	  (NO_BITS_SENT_FAST_2_INT_28 and not NO_BITS_SENT_FAST_3_INT_29) or 
	  (N_24_I_L1 and NO_BITS_SENT_FAST_3_INT_29);
  N_24_I_L1 <= (not NO_BITS_SENT_2_REP1_INT_36 and not NO_BITS_SENT_FAST_1_INT_27) or 
	  (not NO_BITS_SENT_0_REP1_INT_37 and not NO_BITS_SENT_2_REP1_INT_36);
  un1_clk1x_enable10_2_i <= (not UN1_CLK1X_ENABLE10_2_0) or 
	  (WRN2 and not WRN1);
  CLKDIV(3) <= CLKDIV_I(3);
  NN_1 <= '0';
  NN_2 <= '1';
  tsr_7 <= TSR_7_INT_25;
  no_bits_sent_fast(0) <= NO_BITS_SENT_FAST_0_INT_26;
  no_bits_sent_fast(1) <= NO_BITS_SENT_FAST_1_INT_27;
  no_bits_sent_fast(2) <= NO_BITS_SENT_FAST_2_INT_28;
  no_bits_sent_fast(3) <= NO_BITS_SENT_FAST_3_INT_29;
  no_bits_sent(0) <= NO_BITS_SENT_0_INT_30;
  no_bits_sent(1) <= NO_BITS_SENT_1_INT_31;
  no_bits_sent(2) <= NO_BITS_SENT_2_INT_32;