5_1.par

UART 串口程序

Lattice Place and Route Report for Design "uart_v_map.ncd"
Tue Jul 17 10:48:30 2007

PAR: Place And Route ispLever_v61_PROD_Build (37).
Command line: D:/program/isplever/ispfpga\bin\nt\par -f uart_v.p2t uart_v_map.ncd uart_v.dir
uart_v.prf
Preference file: uart_v.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file uart_v_map.ncd.
Design name: uart
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP3C
Package:     TQFP100
Speed:       3
Loading device for application par from file 'mg5g19x26.nph' in environment
D:/program/isplever/ispfpga.
Package: Version 1.40, Status: FINAL
Speed Hardware Data: version 9.999


Ignore Preference Error(s):  Yes
Dumping design to file C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/neo_2.
Device utilization summary:


   PIO               27/160          16% used
                     27/62           43% bonded

   IOLOGIC           21/160          13% used
   SLICE             43/1536          2% used

   GSR                1/1           100% used


Number of Signals: 146
Number of Connections: 371
The following 3 signals are selected to use the primary clock routing resources:
    u1_clkdiv_3 (driver: u1/SLICE_7, clk load #: 17)
    u2/clkdivZ0Z_3 (driver: u2/SLICE_16, clk load #: 14)
    clk16x_c (driver: clk16x, clk load #: 12)

The following 1 signal is selected to use the DCS clock routing resource:
    clk16x_c (driver: clk16x, clk load #: 12)

The following 1 signal is selected to use the secondary clock routing resource:
    wrn_c (driver: wrn, clk load #: 8, sr load #: 0, ce load #: 0)

Signal rst_c is selected as Global Set/Reset.
Starting Placer Phase 0.
..........
Finished Placer Phase 0.  REAL time: 2 secs 

Starting Placer Phase 1.
Placer score = 753766.
.............................
Placer score = 63967.
Finished Placer Phase 1.  REAL time: 22 secs 

Starting Placer Phase 2.
.
Placer score =  63806
Finished Placer Phase 2.  REAL time: 22 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 2 out of 4 (50%)
  PLL        : 0 out of 2 (0%)
  DCS        : 3 out of 8 (37%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "u1_clkdiv_3" from ROUTING "R11C5B.Q0", driver "u1/SLICE_7", clk load = 17
  PRIMARY "u2/clkdivZ0Z_3" from ROUTING "R9C24A.Q1", driver "u2/SLICE_16", clk load = 14
  PRIMARY DCS "clk16x_c" from CLK_PIN "19", driver "clk16x", clk load = 12
  SECONDARY "wrn_c" from CLK_PIN "93", driver "wrn", clk load = 8, ce load = 0, sr load = 0

  PRIMARY  : 3 out of 4 (75%)
     DCS   : 1 out of 2 (50%)
  SECONDARY: 1 out of 4 (25%)

--------------- End of Clock Report ---------------


Total placer CPU time: 21 secs 

Dumping design to file uart_v.dir/5_1.ncd.

0 connections routed; 374 unrouted.
Starting router resource preassignment
Clock Skew Minimization: OFF
Completed router resource preassignment. Real time: 23 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
374 successful; 0 unrouted; (427044) real time: 24 secs 
Dumping design to file uart_v.dir/5_1.ncd.
End of iteration 2
374 successful; 0 unrouted; (426449) real time: 25 secs 
Dumping design to file uart_v.dir/5_1.ncd.
End of iteration 3
374 successful; 0 unrouted; (426449) real time: 26 secs 
End of iteration 4
374 successful; 0 unrouted; (426449) real time: 27 secs 
End of iteration 5
374 successful; 0 unrouted; (426449) real time: 28 secs 
End of iteration 6
374 successful; 0 unrouted; (426449) real time: 30 secs 
Giving up.
Total CPU time 28 secs 
Total REAL time: 30 secs 
Completely routed.
End of route.  374 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.
Timing score: 426449 

Total REAL time to completion: 30 secs 


All signals are completely routed.


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