uart.testbench

UART 串口程序

//----------------------------------------------------------------------
// Automatically Generated Test Bench -- Jagadeesh Vasudevamurthy
// Generated on Tue Jul 17 10:47:45 2007

// To prove RTL and Mapped circuit are equivalent for Altera do the following
// rm -rf inca_libs
// SET Q=X:/Altera/quartus_II60_pc 
// SET ATOMS=stratixii_atoms.v 
// ncverilog +licq_all uart.vt  uart.v  uart.vm  -v %Q%/eda/sim_lib/nopli.v -v %Q%/eda/sim_lib/220model.v -v %Q%/eda/sim_lib/%ATOMS% -v %Q%/eda/sim_lib/altera_mf.v

// To prove RTL and Mapped circuit are equivalent for Xilinx do the following
// rm -rf inca_libs
// ncverilog  +nclicq uart.vt  uart.v  uart.vm  X:/Xilinx/m82i/verilog/src/glbl.v  -y X:/Xilinx/m82i/verilog/src/unisims +libext+.v
//----------------------------------------------------------------------
`timescale 100 ps/100 ps
`define jag 1
module test_bench;
    parameter CLKPER = 1000;
    parameter NUMSIM = 1000;

    wire  [7:0] dout;
    wire  [7:0] dout_rtl;
    wire data_ready;
    wire data_ready_rtl;
    wire framing_error;
    wire framing_error_rtl;
    wire parity_error;
    wire parity_error_rtl;
    reg rxd;
    reg clk16x;
    reg rst;
    reg rdn;
    reg   [7:0] din;
    wire tbre;
    wire tbre_rtl;
    wire tsre;
    wire tsre_rtl;
    reg wrn;
    wire sdo;
    wire sdo_rtl;

    integer i;
    integer numerrors;
    integer vecnum;

    uart_rtl reference(.rxd(rxd),.rst(rst),.rdn(rdn),.din(din),.wrn(wrn),.clk16x(clk16x),.dout(dout_rtl),.data_ready(data_ready_rtl),.framing_error(framing_error_rtl),.parity_error(parity_error_rtl),.tbre(tbre_rtl),.tsre(tsre_rtl),.sdo(sdo_rtl));
    uart         impl(.rxd(rxd),.rst(rst),.rdn(rdn),.din(din),.wrn(wrn),.clk16x(clk16x),.dout(dout),.data_ready(data_ready),.framing_error(framing_error),.parity_error(parity_error),.tbre(tbre),.tsre(tsre),.sdo(sdo));

    initial clk16x = 0;
    always #(CLKPER / 2) clk16x = ~clk16x;

    initial
    begin
        vecnum = 0;
        numerrors = 0;

        $display("Beginning Simulation..."); 
        $display("         vector rxd rst rdn din wrn dout_rtl data_ready_rtl framing_error_rtl parity_error_rtl tbre_rtl tsre_rtl sdo_rtl dout data_ready framing_error parity_error tbre tsre sdo ");   
    end
    always 
    begin 

        @(posedge clk16x);
            clk16x = ~clk16x;
            rxd = $random;
            rst = $random;
            rdn = $random;
            din = $random;
            wrn = $random;

//------------comparing 0 output dout-----------
        @(negedge clk16x);
            if (dout_rtl == dout)
                begin
                    $display(" %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, dout_rtl, dout);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(dout ^ dout) === 1'bx) && (|(dout_rtl ^ dout) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, dout_rtl, dout);
                    end
                end
//------------comparing 1 output data_ready-----------
        @(negedge clk16x);
            if (data_ready_rtl == data_ready)
                begin
                    $display(" %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, data_ready_rtl, data_ready);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(data_ready ^ data_ready) === 1'bx) && (|(data_ready_rtl ^ data_ready) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, data_ready_rtl, data_ready);
                    end
                end
//------------comparing 2 output framing_error-----------
        @(negedge clk16x);
            if (framing_error_rtl == framing_error)
                begin
                    $display(" %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, framing_error_rtl, framing_error);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(framing_error ^ framing_error) === 1'bx) && (|(framing_error_rtl ^ framing_error) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, framing_error_rtl, framing_error);
                    end
                end
//------------comparing 3 output parity_error-----------
        @(negedge clk16x);
            if (parity_error_rtl == parity_error)
                begin
                    $display(" %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, parity_error_rtl, parity_error);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(parity_error ^ parity_error) === 1'bx) && (|(parity_error_rtl ^ parity_error) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, parity_error_rtl, parity_error);
                    end
                end
//------------comparing 4 output tbre-----------
        @(negedge clk16x);
            if (tbre_rtl == tbre)
                begin
                    $display(" %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, tbre_rtl, tbre);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(tbre ^ tbre) === 1'bx) && (|(tbre_rtl ^ tbre) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, tbre_rtl, tbre);
                    end
                end
//------------comparing 5 output tsre-----------
        @(negedge clk16x);
            if (tsre_rtl == tsre)
                begin
                    $display(" %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, tsre_rtl, tsre);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(tsre ^ tsre) === 1'bx) && (|(tsre_rtl ^ tsre) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, tsre_rtl, tsre);
                    end
                end
//------------comparing 6 output sdo-----------
        @(negedge clk16x);
            if (sdo_rtl == sdo)
                begin
                    $display(" %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, sdo_rtl, sdo);
                    // Remove the above comment if you want to see test vectors and output
                    vecnum = vecnum;
                end
                else 
                begin
                    //Note that x^1 = x, 0|x = x and 1|x = 1
                    //This formula is invented by Vijay 
                    // The Mapped net must not produce x	
                    if ( !(|(sdo ^ sdo) === 1'bx) && (|(sdo_rtl ^ sdo) === 1'bx) )   
                        $display("ERROR IS OK") ;
                    else 
                        numerrors = numerrors + 1;  
                    begin
                        $display("ERROR  %d %d %d %d %d %d %d %d ", vecnum,rxd, rst, rdn, din, wrn, sdo_rtl, sdo);
                    end
                end
//------------Reporting Errors-----------
        vecnum = vecnum + 1;
        if (vecnum >= NUMSIM)
        begin
            case (numerrors)
                0 : $display("Good! End of Good Simulation."); 
                default : $display("%0d ERRORS! End of Faulty Simulation.", numerrors); 
            endcase
            #1000 $finish; 
        end
    end
endmodule