📄 uart_v.twr
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Lattice TRACE Report, Version ispLever_v61_PROD_Build (37)
Tue Jul 17 10:49:01 2007
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -o checkpnt.twr uart_v.ncd uart_v.prf
Design file: uart_v.ncd
Preference file: uart_v.prf
Device,speed: LFXP3C,3
Report level: verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "clk16x" 177.054000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.729ns
The internal maximum frequency of the following component is 521.376 MHz
Logical Details: Cell type Pin type Component name
Source: FSLICE Clock u2/SLICE_17
Destination: FSLICE Data in u2/SLICE_17
Delay: 1.918ns -- based on Minimum Pulse Width
Report: 521.376MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "u1_clkdiv_3" 360.750000 MHz ;
105 items scored, 74 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 2.374ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u1/no_bits_rcvdZ0Z_2 (from u1_clkdiv_3 +)
Destination: FF Unknown u1_rbrio_5 (to u1_clkdiv_3 +)
Delay: 5.013ns (19.1% logic, 80.9% route), 2 logic levels.
Constraint Details:
5.013ns physical path delay u1/SLICE_9 to dout_5_MGIOL exceeds
2.772ns delay constraint less
0.186ns skew and
-0.053ns CE_SET requirement (totaling 2.639ns) by 2.374ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.576 R3C12D.CLK to R3C12D.Q0 u1/SLICE_9 (from u1_clkdiv_3)
ROUTE 7 1.466 R3C12D.Q0 to R2C12C.A1 u1_no_bits_rcvd_2
CTOF_DEL --- 0.382 R2C12C.A1 to R2C12C.F1 u1/SLICE_1
ROUTE 10 2.589 R2C12C.F1 to IOL_L3A.CE u1_parity8 (to u1_clkdiv_3)
--------
5.013 (19.1% logic, 80.9% route), 2 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
4.880ns R11C5B.Q0 to R3C12D.CLK
Destination Clock:
Delay Connection
4.694ns R11C5B.Q0 to IOL_L3A.CLK
Warning: 194.326MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clk16x_c" 364.564000 MHz ;
61 items scored, 38 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 7.810ns
and exceeds 5.647ns delay constraint requirement for source clock "u2/clkdivZ0Z_3" by 4.906ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u2/no_bits_sentZ0Z_2 (from u2/clkdivZ0Z_3 +)
Destination: FF Unknown u2_tbreio (to M5GDCS10_clk16x_c +)
Delay: 5.438ns (24.6% logic, 75.4% route), 3 logic levels.
Constraint Details:
5.438ns physical path delay u2/SLICE_23 to tbre_MGIOL exceeds
2.743ns delay constraint less
5.168ns skew and
-0.053ns CE_SET requirement (totaling -2.372ns) by 7.810ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.576 R2C17C.CLK to R2C17C.Q0 u2/SLICE_23 (from u2/clkdivZ0Z_3)
ROUTE 8 1.334 R2C17C.Q0 to R3C17A.C1 u2_no_bits_sent_2
CTOF_DEL --- 0.382 R3C17A.C1 to R3C17A.F1 u2/SLICE_30
ROUTE 2 0.929 R3C17A.F1 to R3C16C.C1 u2/un1_clk1x_enable10_2Z0Z_0
CTOF_DEL --- 0.382 R3C16C.C1 to R3C16C.F1 u2/SLICE_25
ROUTE 1 1.835 R3C16C.F1 to IOL_T17A.CE u2_un1_clk1x_enable10_2_i (to M5GDCS10_clk16x_c)
--------
5.438 (24.6% logic, 75.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.850 19.PAD to 19.PADDI clk16x
ROUTE 3 2.376 19.PADDI to URDCS0.CLK0 clk16x_c
MUX_DEL --- 0.490 URDCS0.CLK0 to URDCS0.DCSOUT M5GDCS10
ROUTE 5 0.691 URDCS0.DCSOUT to R9C24A.CLK M5GDCS10_clk16x_c
REG_DEL --- 0.576 R9C24A.CLK to R9C24A.Q1 u2/SLICE_16
ROUTE 15 4.406 R9C24A.Q1 to R2C17C.CLK u2/clkdivZ0Z_3
--------
9.389 (20.4% logic, 79.6% route), 3 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.850 19.PAD to 19.PADDI clk16x
ROUTE 3 2.376 19.PADDI to URDCS0.CLK0 clk16x_c
MUX_DEL --- 0.490 URDCS0.CLK0 to URDCS0.DCSOUT M5GDCS10
ROUTE 5 0.505 URDCS0.DCSOUT to IOL_T17A.CLK M5GDCS10_clk16x_c
--------
4.221 (31.7% logic, 68.3% route), 2 logic levels.
Warning: 94.760MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "u2/clkdivZ0Z_3" 177.054000 MHz ;
148 items scored, 97 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'wrn_c' and net 'u2/clkdivZ0Z_3' not
computed: nets may not be related
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 2.580ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u2/no_bits_sent_fastZ0Z_1 (from u2/clkdivZ0Z_3 +)
Destination: FF Unknown u2_sdoio (to u2/clkdivZ0Z_3 -)
Delay: 5.234ns (25.6% logic, 74.4% route), 3 logic levels.
Constraint Details:
5.234ns physical path delay u2/SLICE_26 to sdo_MGIOL exceeds
2.823ns delay constraint less
0.186ns skew and
-0.017ns CE_SET requirement (totaling 2.654ns) by 2.580ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.576 R3C16D.CLK to R3C16D.Q1 u2/SLICE_26 (from u2/clkdivZ0Z_3)
ROUTE 6 1.549 R3C16D.Q1 to R2C16C.C0 u2_no_bits_sent_fast_1
CTOF_DEL --- 0.382 R2C16C.C0 to R2C16C.F0 SLICE_35
ROUTE 1 0.984 R2C16C.F0 to R2C16C.A1 u2_un1_no_bits_sent_3_p4
CTOF_DEL --- 0.382 R2C16C.A1 to R2C16C.F1 SLICE_35
ROUTE 1 1.361 R2C16C.F1 to IOL_T16A.CE u2_N_23_i (to u2/clkdivZ0Z_3)
--------
5.234 (25.6% logic, 74.4% route), 3 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
4.406ns R9C24A.Q1 to R3C16D.CLK
Destination Clock:
Delay Connection
4.220ns R9C24A.Q1 to IOL_T16A.CLK
Warning: 92.541MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "clk16x" 177.054000 MHz | | |
; | 177.054 MHz| 521.376 MHz| 0
| | |
FREQUENCY NET "u1_clkdiv_3" 360.750000 | | |
MHz ; | 360.750 MHz| 194.326 MHz| 2
| | |
FREQUENCY NET "clk16x_c" 364.564000 MHz | | |
; | 364.564 MHz| 94.760 MHz| 3
| | |
FREQUENCY NET "u2/clkdivZ0Z_3" | | |
177.054000 MHz ; | 177.054 MHz| 92.541 MHz| 3
| | |
----------------------------------------------------------------------------
3 preferences not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
u1_parity8 | 10| 40| 19.14%
| | |
u2/parityZ0Z7 | 8| 31| 14.83%
| | |
u2/N_24_iZ0 | 5| 30| 14.35%
| | |
u1_parity7 | 7| 28| 13.40%
| | |
----------------------------------------------------------------------------
Timing summary:
---------------
Timing errors: 209 Score: 426449
Cumulative negative slack: 322590
Constraints cover 314 paths, 8 nets, and 336 connections (89.8% coverage)
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