📄 top.rpt
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# !_LC3_B4 & _LC5_B4;
-- Node name is '|POC3:25|~326~1'
-- Equation name is '_LC6_C5', type is buried
-- synthesized logic cell
_LC6_C5 = LCELL( _EQ018);
_EQ018 = _LC3_B4
# !RW
# !_LC1_B4;
-- Node name is '|POC3:25|~530~1'
-- Equation name is '_LC3_B4', type is buried
-- synthesized logic cell
_LC3_B4 = LCELL( _EQ019);
_EQ019 = !A0 & !A1 & !A2 & CS;
-- Node name is '|POC3:25|:644'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ020);
_EQ020 = _LC3_B4 & _LC4_B6 & !RW
# _LC7_B4;
-- Node name is '|POC3:25|:646'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = LCELL( _EQ021);
_EQ021 = _LC1_B4 & _LC1_B8 & !RW;
-- Node name is '|POC3:25|:658'
-- Equation name is '_LC1_C5', type is buried
!_LC1_C5 = _LC1_C5~NOT;
_LC1_C5~NOT = LCELL( _EQ022);
_EQ022 = _LC3_B4 & !RW
# _LC1_B4 & !RW;
-- Node name is '|POC3:25|:659'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ023);
_EQ023 = _LC3_B4 & _LC5_B4 & !RW
# _LC2_B4;
-- Node name is '|POC3:25|:661'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ024);
_EQ024 = _LC1_B4 & _LC8_B4 & !RW;
-- Node name is '|POC3:25|:674'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ025);
_EQ025 = _LC3_B4 & _LC8_A2 & !RW
# _LC7_A2;
-- Node name is '|POC3:25|:676'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ026);
_EQ026 = _LC1_B4 & _LC6_A2 & !RW;
-- Node name is '|POC3:25|:689'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ027);
_EQ027 = _LC3_B4 & _LC4_A2 & !RW
# _LC2_A2;
-- Node name is '|POC3:25|:691'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ028);
_EQ028 = _LC1_A2 & _LC1_B4 & !RW;
-- Node name is '|POC3:25|:704'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = LCELL( _EQ029);
_EQ029 = _LC3_B4 & _LC7_C12 & !RW
# _LC5_C12;
-- Node name is '|POC3:25|:706'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ030);
_EQ030 = _LC1_B4 & _LC1_C12 & !RW;
-- Node name is '|POC3:25|:719'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = LCELL( _EQ031);
_EQ031 = _LC3_B4 & _LC4_C12 & !RW
# _LC2_C12;
-- Node name is '|POC3:25|:721'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ032);
_EQ032 = _LC1_B4 & _LC3_C12 & !RW;
-- Node name is '|POC3:25|:734'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = LCELL( _EQ033);
_EQ033 = _LC3_B4 & _LC8_C5 & !RW
# _LC3_C5;
-- Node name is '|POC3:25|:736'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = LCELL( _EQ034);
_EQ034 = _LC1_B4 & _LC5_C5 & !RW;
-- Node name is '|POC3:25|:749'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ035);
_EQ035 = _LC1_B4 & _LC7_C5 & !RW
# _LC3_B6;
-- Node name is '|POC3:25|:750'
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ036);
_EQ036 = _LC3_B4 & _LC5_B6 & !RW;
-- Node name is '|POC3:25|~1040~1'
-- Equation name is '_LC1_B4', type is buried
-- synthesized logic cell
_LC1_B4 = LCELL( _EQ037);
_EQ037 = A0 & !A1 & !A2 & CS;
-- Node name is '|POC3:25|:1040'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = LCELL( _EQ038);
_EQ038 = _LC1_B4 & RW;
-- Node name is '|POC3:25|:1121'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = LCELL( _EQ039);
_EQ039 = _LC7_B6 & !_LC8_B6;
-- Node name is '|POC3:25|:1132'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ040);
_EQ040 = _LC2_B6 & !_LC7_B6
# _LC8_B6;
-- Node name is '|POC3:25|:1302'
-- Equation name is '_LC1_B6', type is buried
!_LC1_B6 = _LC1_B6~NOT;
_LC1_B6~NOT = LCELL( _EQ041);
_EQ041 = _LC8_B6
# !_LC7_B6
# !_LC5_B6;
-- Node name is '|74193:2|~28~1' = '|74193:2|BON~1'
-- Equation name is '_LC7_B20', type is buried
-- synthesized logic cell
_LC7_B20 = LCELL( _EQ042);
_EQ042 = !CLK
# _LC2_B20
# _LC2_B19
# _LC6_B20;
-- Node name is '|74193:2|:26' = '|74193:2|QA'
-- Equation name is '_LC2_B19', type is buried
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = DFFE( _LC2_B19, _LC1_B19, !_LC2_B6, VCC, VCC);
-- Node name is '|74193:2|:25' = '|74193:2|QB'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = DFFE(!_LC2_B20, !_LC1_B20, !_LC2_B6, VCC, VCC);
-- Node name is '|74193:2|:24' = '|74193:2|QC'
-- Equation name is '_LC6_B20', type is buried
!_LC6_B20 = _LC6_B20~NOT;
_LC6_B20~NOT = DFFE( _LC6_B20, !_LC5_B20, !_LC2_B6, VCC, VCC);
-- Node name is '|74193:2|:23' = '|74193:2|QD'
-- Equation name is '_LC8_B19', type is buried
_LC8_B19 = DFFE(!_LC8_B19, !_LC4_B20, !_LC2_B6, VCC, VCC);
-- Node name is '|74193:2|:6'
-- Equation name is '_LC1_B20', type is buried
!_LC1_B20 = _LC1_B20~NOT;
_LC1_B20~NOT = LCELL( _EQ043);
_EQ043 = _LC2_B19
# !CLK
# !_LC3_B20;
-- Node name is '|74193:2|:22'
-- Equation name is '_LC4_B20', type is buried
!_LC4_B20 = _LC4_B20~NOT;
_LC4_B20~NOT = LCELL( _EQ044);
_EQ044 = _LC2_B19
# _LC1_B19
# _LC2_B20
# _LC6_B20;
-- Node name is '|74193:2|:50'
-- Equation name is '_LC5_B20', type is buried
!_LC5_B20 = _LC5_B20~NOT;
_LC5_B20~NOT = LCELL( _EQ045);
_EQ045 = !CLK
# !_LC3_B20
# _LC2_B19
# _LC2_B20;
-- Node name is ':3'
-- Equation name is '_LC3_B20', type is buried
!_LC3_B20 = _LC3_B20~NOT;
_LC3_B20~NOT = LCELL( _EQ046);
_EQ046 = !_LC2_B6 & _LC8_B20;
-- Node name is ':4'
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = LCELL( _EQ047);
_EQ047 = !CLK
# !_LC3_B20;
-- Node name is ':11'
-- Equation name is '_LC8_B20', type is buried
!_LC8_B20 = _LC8_B20~NOT;
_LC8_B20~NOT = LCELL( _EQ048);
_EQ048 = _LC3_B20 & _LC7_B20 & RESET
# _LC3_B20 & _LC8_B19 & RESET;
Project Information d:\yuhui\top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,945K
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