📄 top.rpt
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- 2 - B 04 AND2 1 2 0 1 |POC3:25|:661
- 5 - A 02 OR2 1 3 1 0 |POC3:25|:674
- 7 - A 02 AND2 1 2 0 1 |POC3:25|:676
- 3 - A 02 OR2 1 3 1 0 |POC3:25|:689
- 2 - A 02 AND2 1 2 0 1 |POC3:25|:691
- 6 - C 12 OR2 1 3 1 0 |POC3:25|:704
- 5 - C 12 AND2 1 2 0 1 |POC3:25|:706
- 8 - C 12 OR2 1 3 1 0 |POC3:25|:719
- 2 - C 12 AND2 1 2 0 1 |POC3:25|:721
- 4 - C 05 OR2 1 3 1 0 |POC3:25|:734
- 3 - C 05 AND2 1 2 0 1 |POC3:25|:736
- 2 - C 05 OR2 1 3 1 0 |POC3:25|:749
- 3 - B 06 AND2 1 2 0 1 |POC3:25|:750
- 1 - B 04 AND2 s 4 0 0 12 |POC3:25|~1040~1
- 6 - B 06 AND2 1 1 0 1 |POC3:25|:1040
- 4 - B 06 AND2 0 2 0 1 |POC3:25|:1121
- 2 - B 06 OR2 0 2 1 5 |POC3:25|:1132
- 1 - B 06 OR2 ! 0 3 1 0 |POC3:25|:1302
- 3 - B 20 AND2 ! 0 2 0 4 :3
- 1 - B 19 OR2 1 1 0 2 :4
- 8 - B 20 OR2 ! 1 3 1 2 :11
- 1 - B 20 OR2 ! 1 2 0 1 |74193:2|:6
- 4 - B 20 OR2 ! 0 4 0 1 |74193:2|:22
- 8 - B 19 DFFE 0 2 0 1 |74193:2|QD (|74193:2|:23)
- 6 - B 20 DFFE ! 0 2 0 2 |74193:2|QC (|74193:2|:24)
- 2 - B 20 DFFE 0 2 0 3 |74193:2|QB (|74193:2|:25)
- 2 - B 19 DFFE ! 0 2 0 4 |74193:2|QA (|74193:2|:26)
- 7 - B 20 OR2 s 1 3 0 1 |74193:2|BON~1 (|74193:2|~28~1)
- 5 - B 20 OR2 ! 1 3 0 1 |74193:2|:50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\yuhui\top.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 2/16( 12%)
B: 6/ 96( 6%) 10/ 48( 20%) 6/ 48( 12%) 1/16( 6%) 5/16( 31%) 2/16( 12%)
C: 8/ 96( 8%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 3/16( 18%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\yuhui\top.rpt
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** CLOCK SIGNALS **
Type Fan-out Name
INPUT 21 CLK
LCELL 2 :4
LCELL 1 |74193:2|:6
LCELL 1 |74193:2|:22
LCELL 1 |74193:2|:50
Device-Specific Information: d:\yuhui\top.rpt
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** CLEAR SIGNALS **
Type Fan-out Name
LCELL 7 |POC3:25|:1132
INPUT 3 RESET
Device-Specific Information: d:\yuhui\top.rpt
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** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
RESET : INPUT;
RW : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(_LC2_C5, !_LC1_C5);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC4_C5, !_LC1_C5);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(_LC8_C12, !_LC1_C5);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(_LC6_C12, !_LC1_C5);
-- Node name is 'D4'
-- Equation name is 'D4', type is bidir
D4 = TRI(_LC3_A2, !_LC1_C5);
-- Node name is 'D5'
-- Equation name is 'D5', type is bidir
D5 = TRI(_LC5_A2, !_LC1_C5);
-- Node name is 'D6'
-- Equation name is 'D6', type is bidir
D6 = TRI(_LC6_B4, !_LC1_C5);
-- Node name is 'D7'
-- Equation name is 'D7', type is bidir
D7 = TRI(_LC4_B4, !_LC1_C5);
-- Node name is 'IRQ'
-- Equation name is 'IRQ', type is output
IRQ = !_LC1_B6;
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = TRI(_LC7_C5, !_LC4_B6);
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = TRI(_LC5_C5, !_LC4_B6);
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = TRI(_LC3_C12, !_LC4_B6);
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = TRI(_LC1_C12, !_LC4_B6);
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = TRI(_LC1_A2, !_LC4_B6);
-- Node name is 'PD5'
-- Equation name is 'PD5', type is output
PD5 = TRI(_LC6_A2, !_LC4_B6);
-- Node name is 'PD6'
-- Equation name is 'PD6', type is output
PD6 = TRI(_LC8_B4, !_LC4_B6);
-- Node name is 'PD7'
-- Equation name is 'PD7', type is output
PD7 = TRI(_LC1_B8, !_LC4_B6);
-- Node name is 'RDY'
-- Equation name is 'RDY', type is output
RDY = _LC8_B20;
-- Node name is 'TR'
-- Equation name is 'TR', type is output
TR = _LC2_B6;
-- Node name is '|POC3:25|:46' = '|POC3:25|BR0'
-- Equation name is '_LC7_C5', type is buried
_LC7_C5 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = D0 & !_LC6_C5
# _LC6_C5 & _LC7_C5;
-- Node name is '|POC3:25|:45' = '|POC3:25|BR1'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = D1 & !_LC6_C5
# _LC5_C5 & _LC6_C5;
-- Node name is '|POC3:25|:44' = '|POC3:25|BR2'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = D2 & !_LC6_C5
# _LC3_C12 & _LC6_C5;
-- Node name is '|POC3:25|:43' = '|POC3:25|BR3'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = D3 & !_LC6_C5
# _LC1_C12 & _LC6_C5;
-- Node name is '|POC3:25|:42' = '|POC3:25|BR4'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = D4 & !_LC6_C5
# _LC1_A2 & _LC6_C5;
-- Node name is '|POC3:25|:41' = '|POC3:25|BR5'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = D5 & !_LC6_C5
# _LC6_A2 & _LC6_C5;
-- Node name is '|POC3:25|:40' = '|POC3:25|BR6'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = D6 & !_LC6_C5
# _LC6_C5 & _LC8_B4;
-- Node name is '|POC3:25|:39' = '|POC3:25|BR7'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = D7 & !_LC6_C5
# _LC1_B8 & _LC6_C5;
-- Node name is '|POC3:25|:28' = '|POC3:25|CURRENT_STATE0'
-- Equation name is '_LC7_B6', type is buried
!_LC7_B6 = _LC7_B6~NOT;
_LC7_B6~NOT = DFFE( _EQ009, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ009 = _LC8_B6
# !_LC7_B6 & !_LC8_B20
# _LC6_B6 & !_LC8_B20
# _LC6_B6 & _LC7_B6;
-- Node name is '|POC3:25|:27' = '|POC3:25|CURRENT_STATE1'
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = DFFE( _EQ010, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ010 = _LC1_B4 & _LC7_B6 & !_LC8_B6 & RW;
-- Node name is '|POC3:25|:38' = '|POC3:25|SR0'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = DFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = D0 & _LC3_B4 & RW
# _LC5_B6 & !RW
# !_LC3_B4 & _LC5_B6;
-- Node name is '|POC3:25|:37' = '|POC3:25|SR1'
-- Equation name is '_LC8_C5', type is buried
_LC8_C5 = DFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = D1 & _LC3_B4 & RW
# _LC8_C5 & !RW
# !_LC3_B4 & _LC8_C5;
-- Node name is '|POC3:25|:36' = '|POC3:25|SR2'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = DFFE( _EQ013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = D2 & _LC3_B4 & RW
# _LC4_C12 & !RW
# !_LC3_B4 & _LC4_C12;
-- Node name is '|POC3:25|:35' = '|POC3:25|SR3'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = DFFE( _EQ014, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = D3 & _LC3_B4 & RW
# _LC7_C12 & !RW
# !_LC3_B4 & _LC7_C12;
-- Node name is '|POC3:25|:34' = '|POC3:25|SR4'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = DFFE( _EQ015, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = D4 & _LC3_B4 & RW
# _LC4_A2 & !RW
# !_LC3_B4 & _LC4_A2;
-- Node name is '|POC3:25|:33' = '|POC3:25|SR5'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = DFFE( _EQ016, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = D5 & _LC3_B4 & RW
# _LC8_A2 & !RW
# !_LC3_B4 & _LC8_A2;
-- Node name is '|POC3:25|:32' = '|POC3:25|SR6'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = DFFE( _EQ017, GLOBAL( CLK), VCC, VCC, VCC);
_EQ017 = D6 & _LC3_B4 & RW
# _LC5_B4 & !RW
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