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_EQ014 = D3 & _LC8_C2 & RW
# _LC6_C14 & !RW
# _LC6_C14 & !_LC8_C2;
-- Node name is '|POC6:15|:34' = '|POC6:15|SR4'
-- Equation name is '_LC4_C8', type is buried
_LC4_C8 = DFFE( _EQ015, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = D4 & _LC8_C2 & RW
# _LC4_C8 & !RW
# _LC4_C8 & !_LC8_C2;
-- Node name is '|POC6:15|:33' = '|POC6:15|SR5'
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = DFFE( _EQ016, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = D5 & _LC8_C2 & RW
# _LC8_C8 & !RW
# !_LC8_C2 & _LC8_C8;
-- Node name is '|POC6:15|:32' = '|POC6:15|SR6'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = DFFE( _EQ017, GLOBAL( CLK), VCC, VCC, VCC);
_EQ017 = D6 & _LC8_C2 & RW
# _LC5_C2 & !RW
# _LC5_C2 & !_LC8_C2;
-- Node name is '|POC6:15|~326~1'
-- Equation name is '_LC6_C17', type is buried
-- synthesized logic cell
_LC6_C17 = LCELL( _EQ018);
_EQ018 = _LC8_C2
# !RW
# !_LC3_C2;
-- Node name is '|POC6:15|~530~1'
-- Equation name is '_LC8_C2', type is buried
-- synthesized logic cell
_LC8_C2 = LCELL( _EQ019);
_EQ019 = !A0 & !A1 & !A2 & CS;
-- Node name is '|POC6:15|:644'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ020);
_EQ020 = _LC1_C4 & _LC8_C2 & !RW
# _LC6_C2;
-- Node name is '|POC6:15|:646'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = LCELL( _EQ021);
_EQ021 = _LC1_C10 & _LC3_C2 & !RW;
-- Node name is '|POC6:15|:658'
-- Equation name is '_LC1_C17', type is buried
!_LC1_C17 = _LC1_C17~NOT;
_LC1_C17~NOT = LCELL( _EQ022);
_EQ022 = _LC8_C2 & !RW
# _LC3_C2 & !RW;
-- Node name is '|POC6:15|:659'
-- Equation name is '_LC2_C2', type is buried
_LC2_C2 = LCELL( _EQ023);
_EQ023 = _LC5_C2 & _LC8_C2 & !RW
# _LC4_C2;
-- Node name is '|POC6:15|:661'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = LCELL( _EQ024);
_EQ024 = _LC1_C2 & _LC3_C2 & !RW;
-- Node name is '|POC6:15|:674'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ025);
_EQ025 = _LC8_C2 & _LC8_C8 & !RW
# _LC7_C8;
-- Node name is '|POC6:15|:676'
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = LCELL( _EQ026);
_EQ026 = _LC3_C2 & _LC6_C8 & !RW;
-- Node name is '|POC6:15|:689'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ027);
_EQ027 = _LC4_C8 & _LC8_C2 & !RW
# _LC2_C8;
-- Node name is '|POC6:15|:691'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ028);
_EQ028 = _LC3_C2 & _LC3_C8 & !RW;
-- Node name is '|POC6:15|:704'
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = LCELL( _EQ029);
_EQ029 = _LC6_C14 & _LC8_C2 & !RW
# _LC5_C14;
-- Node name is '|POC6:15|:706'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = LCELL( _EQ030);
_EQ030 = _LC3_C2 & _LC8_C14 & !RW;
-- Node name is '|POC6:15|:719'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = LCELL( _EQ031);
_EQ031 = _LC4_C14 & _LC8_C2 & !RW
# _LC2_C14;
-- Node name is '|POC6:15|:721'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = LCELL( _EQ032);
_EQ032 = _LC3_C2 & _LC3_C14 & !RW;
-- Node name is '|POC6:15|:734'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = LCELL( _EQ033);
_EQ033 = _LC8_C2 & _LC8_C17 & !RW
# _LC7_C17;
-- Node name is '|POC6:15|:736'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = LCELL( _EQ034);
_EQ034 = _LC2_C17 & _LC3_C2 & !RW;
-- Node name is '|POC6:15|:749'
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = LCELL( _EQ035);
_EQ035 = _LC3_C2 & _LC3_C17 & !RW
# _LC2_C4;
-- Node name is '|POC6:15|:750'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ036);
_EQ036 = _LC7_C4 & _LC8_C2 & !RW;
-- Node name is '|POC6:15|~1045~1'
-- Equation name is '_LC3_C2', type is buried
-- synthesized logic cell
_LC3_C2 = LCELL( _EQ037);
_EQ037 = A0 & !A1 & !A2 & CS;
-- Node name is '|POC6:15|:1045'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ038);
_EQ038 = _LC3_C2 & RW;
-- Node name is '|POC6:15|:1156'
-- Equation name is '_LC1_C4', type is buried
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ039);
_EQ039 = _LC4_C4
# !_LC5_C4;
-- Node name is '|POC6:15|:1286'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = LCELL( _LC4_C4);
-- Node name is '|POC6:15|:1334'
-- Equation name is '_LC6_C4', type is buried
!_LC6_C4 = _LC6_C4~NOT;
_LC6_C4~NOT = LCELL( _EQ040);
_EQ040 = _LC4_C4
# !_LC5_C4
# !_LC7_C4;
-- Node name is '|PRINT2:7|:7' = '|PRINT2:7|COUNT0'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = DFFE( _EQ041, GLOBAL( CLK), VCC, VCC, !_LC2_C3);
_EQ041 = _LC1_C3 & _LC3_C3 & _LC4_C3
# !_LC1_C3 & _LC3_C3 & !_LC4_C3;
-- Node name is '|PRINT2:7|:6' = '|PRINT2:7|COUNT1'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = DFFE( _EQ042, GLOBAL( CLK), VCC, VCC, !_LC2_C3);
_EQ042 = _LC3_C3 & _LC5_C3;
-- Node name is '|PRINT2:7|PRINT~1'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = DFFE( _EQ043, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ043 = !_LC6_C3 & _LC7_C3
# !_LC4_C3 & _LC7_C3
# !_LC7_C3 & _LC8_C4;
-- Node name is '|PRINT2:7|:1'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = DFFE( _EQ044, GLOBAL( CLK), VCC, VCC, !_LC2_C3);
_EQ044 = _LC7_C3 & _LC8_C3
# !_LC7_C3 & !_LC8_C4;
-- Node name is '|PRINT2:7|:103'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = LCELL( _EQ045);
_EQ045 = !_LC4_C3 & _LC6_C3
# !_LC1_C3 & _LC4_C3 & !_LC6_C3
# _LC1_C3 & _LC6_C3;
-- Node name is '|PRINT2:7|:127'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = LCELL( _EQ046);
_EQ046 = _LC1_C3
# _LC4_C3 & _LC6_C3;
-- Node name is '|PRINT2:7|:175'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ047);
_EQ047 = !_LC6_C3 & _LC7_C3
# !_LC4_C3 & _LC7_C3;
Project Information d:\study\kb\pocr.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,924K
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