📄 pocr.rpt
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Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 04 DFFE + 0 3 0 4 |POC6:15|CURRENT_STATE1 (|POC6:15|:27)
- 5 - C 04 DFFE + ! 0 3 0 3 |POC6:15|CURRENT_STATE0 (|POC6:15|:28)
- 5 - C 02 DFFE + 1 2 0 1 |POC6:15|SR6 (|POC6:15|:32)
- 8 - C 08 DFFE + 1 2 0 1 |POC6:15|SR5 (|POC6:15|:33)
- 4 - C 08 DFFE + 1 2 0 1 |POC6:15|SR4 (|POC6:15|:34)
- 6 - C 14 DFFE + 1 2 0 1 |POC6:15|SR3 (|POC6:15|:35)
- 4 - C 14 DFFE + 1 2 0 1 |POC6:15|SR2 (|POC6:15|:36)
- 8 - C 17 DFFE + 1 2 0 1 |POC6:15|SR1 (|POC6:15|:37)
- 7 - C 04 DFFE + 1 2 0 2 |POC6:15|SR0 (|POC6:15|:38)
- 1 - C 10 DFFE + 0 2 1 1 |POC6:15|BR7 (|POC6:15|:39)
- 1 - C 02 DFFE + 0 2 1 1 |POC6:15|BR6 (|POC6:15|:40)
- 6 - C 08 DFFE + 0 2 1 1 |POC6:15|BR5 (|POC6:15|:41)
- 3 - C 08 DFFE + 0 2 1 1 |POC6:15|BR4 (|POC6:15|:42)
- 8 - C 14 DFFE + 0 2 1 1 |POC6:15|BR3 (|POC6:15|:43)
- 3 - C 14 DFFE + 0 2 1 1 |POC6:15|BR2 (|POC6:15|:44)
- 2 - C 17 DFFE + 0 2 1 1 |POC6:15|BR1 (|POC6:15|:45)
- 3 - C 17 DFFE + 0 2 1 1 |POC6:15|BR0 (|POC6:15|:46)
- 6 - C 17 OR2 s 1 2 0 8 |POC6:15|~326~1
- 8 - C 02 AND2 s 4 0 0 17 |POC6:15|~530~1
- 7 - C 02 OR2 1 3 1 0 |POC6:15|:644
- 6 - C 02 AND2 1 2 0 1 |POC6:15|:646
- 1 - C 17 OR2 ! 1 2 0 0 |POC6:15|:658
- 2 - C 02 OR2 1 3 1 0 |POC6:15|:659
- 4 - C 02 AND2 1 2 0 1 |POC6:15|:661
- 5 - C 08 OR2 1 3 1 0 |POC6:15|:674
- 7 - C 08 AND2 1 2 0 1 |POC6:15|:676
- 1 - C 08 OR2 1 3 1 0 |POC6:15|:689
- 2 - C 08 AND2 1 2 0 1 |POC6:15|:691
- 7 - C 14 OR2 1 3 1 0 |POC6:15|:704
- 5 - C 14 AND2 1 2 0 1 |POC6:15|:706
- 1 - C 14 OR2 1 3 1 0 |POC6:15|:719
- 2 - C 14 AND2 1 2 0 1 |POC6:15|:721
- 5 - C 17 OR2 1 3 1 0 |POC6:15|:734
- 7 - C 17 AND2 1 2 0 1 |POC6:15|:736
- 4 - C 17 OR2 1 3 1 0 |POC6:15|:749
- 2 - C 04 AND2 1 2 0 1 |POC6:15|:750
- 3 - C 02 AND2 s 4 0 0 11 |POC6:15|~1045~1
- 3 - C 04 AND2 1 1 0 2 |POC6:15|:1045
- 1 - C 04 OR2 ! 0 2 0 1 |POC6:15|:1156
- 8 - C 04 AND2 0 1 0 2 |POC6:15|:1286
- 6 - C 04 OR2 ! 0 3 1 0 |POC6:15|:1334
- 7 - C 03 DFFE + 0 3 0 2 |PRINT2:7|PRINT~1
- 1 - C 03 DFFE + 0 4 0 5 |PRINT2:7|:1
- 6 - C 03 DFFE + 0 3 0 4 |PRINT2:7|COUNT1 (|PRINT2:7|:6)
- 4 - C 03 DFFE + 0 3 0 4 |PRINT2:7|COUNT0 (|PRINT2:7|:7)
- 5 - C 03 OR2 0 3 0 1 |PRINT2:7|:103
- 8 - C 03 OR2 0 3 0 1 |PRINT2:7|:127
- 3 - C 03 OR2 0 3 0 2 |PRINT2:7|:175
- 2 - C 03 SOFT s ! 1 0 0 3 RESET~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\study\kb\pocr.rpt
pocr
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 14/ 96( 14%) 8/ 48( 16%) 5/ 48( 10%) 0/16( 0%) 1/16( 6%) 8/16( 50%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\study\kb\pocr.rpt
pocr
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 21 CLK
Device-Specific Information: d:\study\kb\pocr.rpt
pocr
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 RESET
Device-Specific Information: d:\study\kb\pocr.rpt
pocr
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
RESET : INPUT;
RW : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(_LC4_C17, !_LC1_C17);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC5_C17, !_LC1_C17);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(_LC1_C14, !_LC1_C17);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(_LC7_C14, !_LC1_C17);
-- Node name is 'D4'
-- Equation name is 'D4', type is bidir
D4 = TRI(_LC1_C8, !_LC1_C17);
-- Node name is 'D5'
-- Equation name is 'D5', type is bidir
D5 = TRI(_LC5_C8, !_LC1_C17);
-- Node name is 'D6'
-- Equation name is 'D6', type is bidir
D6 = TRI(_LC2_C2, !_LC1_C17);
-- Node name is 'D7'
-- Equation name is 'D7', type is bidir
D7 = TRI(_LC7_C2, !_LC1_C17);
-- Node name is 'IRQ'
-- Equation name is 'IRQ', type is output
IRQ = !_LC6_C4;
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = TRI(_LC3_C17, !_LC1_C4);
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = TRI(_LC2_C17, !_LC1_C4);
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = TRI(_LC3_C14, !_LC1_C4);
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = TRI(_LC8_C14, !_LC1_C4);
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = TRI(_LC3_C8, !_LC1_C4);
-- Node name is 'PD5'
-- Equation name is 'PD5', type is output
PD5 = TRI(_LC6_C8, !_LC1_C4);
-- Node name is 'PD6'
-- Equation name is 'PD6', type is output
PD6 = TRI(_LC1_C2, !_LC1_C4);
-- Node name is 'PD7'
-- Equation name is 'PD7', type is output
PD7 = TRI(_LC1_C10, !_LC1_C4);
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC2_C3, type is buried.
-- synthesized logic cell
!_LC2_C3 = _LC2_C3~NOT;
_LC2_C3~NOT = LCELL(!RESET);
-- Node name is '|POC6:15|:46' = '|POC6:15|BR0'
-- Equation name is '_LC3_C17', type is buried
_LC3_C17 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = D0 & !_LC6_C17
# _LC3_C17 & _LC6_C17;
-- Node name is '|POC6:15|:45' = '|POC6:15|BR1'
-- Equation name is '_LC2_C17', type is buried
_LC2_C17 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = D1 & !_LC6_C17
# _LC2_C17 & _LC6_C17;
-- Node name is '|POC6:15|:44' = '|POC6:15|BR2'
-- Equation name is '_LC3_C14', type is buried
_LC3_C14 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = D2 & !_LC6_C17
# _LC3_C14 & _LC6_C17;
-- Node name is '|POC6:15|:43' = '|POC6:15|BR3'
-- Equation name is '_LC8_C14', type is buried
_LC8_C14 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = D3 & !_LC6_C17
# _LC6_C17 & _LC8_C14;
-- Node name is '|POC6:15|:42' = '|POC6:15|BR4'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = D4 & !_LC6_C17
# _LC3_C8 & _LC6_C17;
-- Node name is '|POC6:15|:41' = '|POC6:15|BR5'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = D5 & !_LC6_C17
# _LC6_C8 & _LC6_C17;
-- Node name is '|POC6:15|:40' = '|POC6:15|BR6'
-- Equation name is '_LC1_C2', type is buried
_LC1_C2 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = D6 & !_LC6_C17
# _LC1_C2 & _LC6_C17;
-- Node name is '|POC6:15|:39' = '|POC6:15|BR7'
-- Equation name is '_LC1_C10', type is buried
_LC1_C10 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = D7 & !_LC6_C17
# _LC1_C10 & _LC6_C17;
-- Node name is '|POC6:15|:28' = '|POC6:15|CURRENT_STATE0'
-- Equation name is '_LC5_C4', type is buried
!_LC5_C4 = _LC5_C4~NOT;
_LC5_C4~NOT = DFFE( _EQ009, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ009 = _LC4_C4
# _LC3_C4 & _LC5_C4
# !_LC1_C3 & _LC3_C4
# !_LC1_C3 & !_LC5_C4;
-- Node name is '|POC6:15|:27' = '|POC6:15|CURRENT_STATE1'
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = DFFE( _EQ010, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ010 = _LC3_C4 & !_LC4_C4 & _LC5_C4
# !_LC1_C3 & _LC4_C4;
-- Node name is '|POC6:15|:38' = '|POC6:15|SR0'
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = DFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = D0 & _LC8_C2 & RW
# _LC7_C4 & !RW
# _LC7_C4 & !_LC8_C2;
-- Node name is '|POC6:15|:37' = '|POC6:15|SR1'
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = DFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = D1 & _LC8_C2 & RW
# _LC8_C17 & !RW
# !_LC8_C2 & _LC8_C17;
-- Node name is '|POC6:15|:36' = '|POC6:15|SR2'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = DFFE( _EQ013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = D2 & _LC8_C2 & RW
# _LC4_C14 & !RW
# _LC4_C14 & !_LC8_C2;
-- Node name is '|POC6:15|:35' = '|POC6:15|SR3'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = DFFE( _EQ014, GLOBAL( CLK), VCC, VCC, VCC);
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