poc.vhd

用VHDL编写的简单POC（并行输出控制）程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY POC IS
	PORT(
		RESET, CLK, RDY, RW, CS: IN STD_LOGIC;
		IRQ, TR: OUT STD_LOGIC;
		A: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		D: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		PD: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END POC;

ARCHITECTURE ACTION OF POC IS
	TYPE STATE_TYPE IS (WAITPRT, WAITDATA, RESPONSE);
	SIGNAL CURRENT_STATE, NEXT_STATE: STATE_TYPE;
	SIGNAL SR, BR: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
--	PROCESS(CS, RW, BR)
--	BEGIN
--		IF CS = '1' AND RW = '0' THEN
--			D <= BR;
--		ELSE
--			D <= "ZZZZZZZZ";
--		END IF;
--	END PROCESS;
--	PROCESS(CLK)
--	BEGIN
--		IF FALLING_EDGE(CLK) THEN
--		IF CS = '1' AND RW = '1' THEN
--			BR <= D;
--		END IF;
--		END IF;
--	END PROCESS;
	PROCESS(CLK, RESET)
	BEGIN
		IF RESET = '0' THEN
			CURRENT_STATE <= WAITPRT;
		ELSIF FALLING_EDGE(CLK) THEN
			CURRENT_STATE <= NEXT_STATE;
		END IF;
	END PROCESS;

	IRQ <= '0' WHEN SR(7) = '1' AND SR(0) = '1' ELSE '1';
	
	PROCESS(SR, BR, CS, RW, A)
	BEGIN
		IF CS = '1' AND RW = '0' AND A = "000" THEN
			D <= SR;
		ELSIF CS = '1' AND RW = '0' AND A = "001" THEN
			D <= BR;
		ELSE
			D <= "ZZZZZZZZ";
		END IF;
	END PROCESS;

	PROCESS
	BEGIN
		IF FALLING_EDGE(CLK) THEN
		IF CS = '1' AND RW = '1' AND A = "000" THEN
			SR <= D;
		ELSIF CS = '1' AND RW = '1' AND A = "001" THEN
			BR <= D;
		END IF;
		CASE CURRENT_STATE IS
		WHEN WAITDATA =>
			SR(7) <= '1';
		WHEN OTHERS =>
			SR(7) <= '0';
		END CASE;
		END IF;
	END PROCESS;

	PROCESS(CURRENT_STATE, RDY, CS, RW, A, BR)
	BEGIN
		CASE CURRENT_STATE IS
		WHEN WAITPRT =>
			PD <= BR;
			TR <= '0';
			IF RDY = '1' THEN
				NEXT_STATE <= WAITDATA;
			ELSE
				NEXT_STATE <= WAITPRT;
			END IF;
		WHEN WAITDATA =>
			PD <= "00000000";
			TR <= '0';
			IF CS = '1' AND RW = '1' AND A = "001" THEN
				NEXT_STATE <= RESPONSE;
			ELSE
				NEXT_STATE <= WAITDATA;
			END IF;
		WHEN RESPONSE =>
			TR <= '1';
			PD <= BR;
			NEXT_STATE <= WAITPRT;
		END CASE;
	END PROCESS;
		 
END ACTION;