poctest.rpt

用VHDL编写的简单POC（并行输出控制）程序

_LC5_C16 = DFFE( _EQ017, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ017 =  D6 &  _LC3_C21 &  RW
         #  _LC5_C16 & !RW
         # !_LC3_C21 &  _LC5_C16;

-- Node name is '|POC:4|:31' = '|POC:4|SR7' 
-- Equation name is '_LC7_C4', type is buried 
_LC7_C4  = DFFE( _EQ018, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ018 =  _LC3_C4 & !_LC6_C4;

-- Node name is '|POC:4|~128~1' 
-- Equation name is '_LC3_C21', type is buried 
-- synthesized logic cell 
_LC3_C21 = LCELL( _EQ019);
  _EQ019 = !A0 & !A1 & !A2 &  CS;

-- Node name is '|POC:4|:242' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ020);
  _EQ020 =  _LC3_C21 &  _LC7_C4 & !RW
         #  _LC2_C16;

-- Node name is '|POC:4|:244' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ021);
  _EQ021 =  _LC2_C21 &  _LC8_C16 & !RW;

-- Node name is '|POC:4|:256' 
-- Equation name is '_LC1_C23', type is buried 
!_LC1_C23 = _LC1_C23~NOT;
_LC1_C23~NOT = LCELL( _EQ022);
  _EQ022 =  _LC3_C21 & !RW
         #  _LC2_C21 & !RW;

-- Node name is '|POC:4|:257' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = LCELL( _EQ023);
  _EQ023 =  _LC3_C21 &  _LC5_C16 & !RW
         #  _LC3_C16;

-- Node name is '|POC:4|:259' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = LCELL( _EQ024);
  _EQ024 =  _LC2_C21 &  _LC6_C16 & !RW;

-- Node name is '|POC:4|:272' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ025);
  _EQ025 =  _LC3_C21 &  _LC4_C21 & !RW
         #  _LC2_C23;

-- Node name is '|POC:4|:274' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = LCELL( _EQ026);
  _EQ026 =  _LC1_C19 &  _LC2_C21 & !RW;

-- Node name is '|POC:4|:287' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ027);
  _EQ027 =  _LC3_C19 &  _LC3_C21 & !RW
         #  _LC2_C19;

-- Node name is '|POC:4|:289' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ028);
  _EQ028 =  _LC2_C21 &  _LC8_C19 & !RW;

-- Node name is '|POC:4|:302' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ029);
  _EQ029 =  _LC3_C21 &  _LC6_C15 & !RW
         #  _LC4_C15;

-- Node name is '|POC:4|:304' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ030);
  _EQ030 =  _LC2_C21 &  _LC5_C15 & !RW;

-- Node name is '|POC:4|:317' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = LCELL( _EQ031);
  _EQ031 =  _LC2_C15 &  _LC3_C21 & !RW
         #  _LC1_C15;

-- Node name is '|POC:4|:319' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = LCELL( _EQ032);
  _EQ032 =  _LC2_C21 &  _LC8_C15 & !RW;

-- Node name is '|POC:4|:332' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ033);
  _EQ033 =  _LC3_C21 &  _LC6_C23 & !RW
         #  _LC5_C23;

-- Node name is '|POC:4|:334' 
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = LCELL( _EQ034);
  _EQ034 =  _LC2_C21 &  _LC8_C23 & !RW;

-- Node name is '|POC:4|:347' 
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = LCELL( _EQ035);
  _EQ035 =  _LC2_C21 &  _LC6_C5 & !RW
         #  _LC5_C5;

-- Node name is '|POC:4|:348' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = LCELL( _EQ036);
  _EQ036 =  _LC3_C21 &  _LC5_C4 & !RW;

-- Node name is '|POC:4|~576~1' 
-- Equation name is '_LC7_C23', type is buried 
-- synthesized logic cell 
_LC7_C23 = LCELL( _EQ037);
  _EQ037 =  _LC3_C21
         # !RW
         # !_LC2_C21;

-- Node name is '|POC:4|~1044~1' 
-- Equation name is '_LC2_C21', type is buried 
-- synthesized logic cell 
_LC2_C21 = LCELL( _EQ038);
  _EQ038 =  A0 & !A1 & !A2 &  CS;

-- Node name is '|POC:4|:1044' 
-- Equation name is '_LC4_C4', type is buried 
!_LC4_C4 = _LC4_C4~NOT;
_LC4_C4~NOT = LCELL( _EQ039);
  _EQ039 = !RW
         # !_LC2_C21;

-- Node name is '|POC:4|:1136' 
-- Equation name is '_LC7_C16', type is buried 
_LC7_C16 = LCELL( _EQ040);
  _EQ040 =  _LC6_C4 &  _LC8_C16
         # !_LC3_C4 &  _LC8_C16;

-- Node name is '|POC:4|:1145' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = LCELL( _EQ041);
  _EQ041 =  _LC6_C4 &  _LC6_C16
         # !_LC3_C4 &  _LC6_C16;

-- Node name is '|POC:4|:1154' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = LCELL( _EQ042);
  _EQ042 =  _LC1_C19 &  _LC6_C4
         #  _LC1_C19 & !_LC3_C4;

-- Node name is '|POC:4|:1163' 
-- Equation name is '_LC7_C19', type is buried 
_LC7_C19 = LCELL( _EQ043);
  _EQ043 =  _LC6_C4 &  _LC8_C19
         # !_LC3_C4 &  _LC8_C19;

-- Node name is '|POC:4|:1172' 
-- Equation name is '_LC1_C4', type is buried 
_LC1_C4  = LCELL( _EQ044);
  _EQ044 =  _LC5_C15 &  _LC6_C4
         # !_LC3_C4 &  _LC5_C15;

-- Node name is '|POC:4|:1181' 
-- Equation name is '_LC6_C19', type is buried 
_LC6_C19 = LCELL( _EQ045);
  _EQ045 =  _LC6_C4 &  _LC8_C15
         # !_LC3_C4 &  _LC8_C15;

-- Node name is '|POC:4|:1190' 
-- Equation name is '_LC4_C23', type is buried 
_LC4_C23 = LCELL( _EQ046);
  _EQ046 =  _LC6_C4 &  _LC8_C23
         # !_LC3_C4 &  _LC8_C23;

-- Node name is '|POC:4|:1199' 
-- Equation name is '_LC3_C5', type is buried 
_LC3_C5  = LCELL( _EQ047);
  _EQ047 =  _LC6_C4 &  _LC6_C5
         # !_LC3_C4 &  _LC6_C5;

-- Node name is '|POC:4|:1210' 
-- Equation name is '_LC8_C5', type is buried 
!_LC8_C5 = _LC8_C5~NOT;
_LC8_C5~NOT = LCELL(!_LC6_C4);

-- Node name is '|POC:4|:1258' 
-- Equation name is '_LC2_C4', type is buried 
!_LC2_C4 = _LC2_C4~NOT;
_LC2_C4~NOT = LCELL( _EQ048);
  _EQ048 = !_LC7_C4
         # !_LC5_C4;

-- Node name is '|PRTSIM:3|:7' = '|PRTSIM:3|COUNT0' 
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = DFFE( _EQ049, GLOBAL( CLK), !_LC8_C5,  VCC,  RESET);
  _EQ049 =  _LC2_C5 &  _LC7_C5
         # !_LC2_C5 & !_LC7_C5;

-- Node name is '|PRTSIM:3|:6' = '|PRTSIM:3|COUNT1' 
-- Equation name is '_LC4_C5', type is buried 
_LC4_C5  = DFFE( _EQ050, GLOBAL( CLK), !_LC8_C5,  VCC,  RESET);
  _EQ050 = !_LC2_C5 &  _LC4_C5
         #  _LC2_C5 & !_LC4_C5 & !_LC7_C5
         #  _LC4_C5 &  _LC7_C5;

-- Node name is '|PRTSIM:3|:1' 
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = DFFE( _EQ051, GLOBAL( CLK), !_LC8_C5, GLOBAL( RESET),  VCC);
  _EQ051 =  _LC7_C5
         #  _LC2_C5 &  _LC4_C5;



Project Information                               d:\yuhui\poc\poc\poctest.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,865K