📄 poctest.rpt
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- 8 - C 23 DFFE + 0 2 0 2 |POC:4|BR1 (|POC:4|:45)
- 6 - C 05 DFFE + 0 2 0 2 |POC:4|BR0 (|POC:4|:46)
- 3 - C 21 AND2 s 4 0 0 17 |POC:4|~128~1
- 8 - C 04 OR2 1 3 1 0 |POC:4|:242
- 2 - C 16 AND2 1 2 0 1 |POC:4|:244
- 1 - C 23 OR2 ! 1 2 0 0 |POC:4|:256
- 4 - C 16 OR2 1 3 1 0 |POC:4|:257
- 3 - C 16 AND2 1 2 0 1 |POC:4|:259
- 1 - C 21 OR2 1 3 1 0 |POC:4|:272
- 2 - C 23 AND2 1 2 0 1 |POC:4|:274
- 5 - C 19 OR2 1 3 1 0 |POC:4|:287
- 2 - C 19 AND2 1 2 0 1 |POC:4|:289
- 3 - C 15 OR2 1 3 1 0 |POC:4|:302
- 4 - C 15 AND2 1 2 0 1 |POC:4|:304
- 7 - C 15 OR2 1 3 1 0 |POC:4|:317
- 1 - C 15 AND2 1 2 0 1 |POC:4|:319
- 3 - C 23 OR2 1 3 1 0 |POC:4|:332
- 5 - C 23 AND2 1 2 0 1 |POC:4|:334
- 1 - C 05 OR2 1 3 1 0 |POC:4|:347
- 5 - C 05 AND2 1 2 0 1 |POC:4|:348
- 7 - C 23 OR2 s 1 2 0 8 |POC:4|~576~1
- 2 - C 21 AND2 s 4 0 0 12 |POC:4|~1044~1
- 4 - C 04 OR2 ! 1 1 0 1 |POC:4|:1044
- 7 - C 16 OR2 0 3 1 0 |POC:4|:1136
- 1 - C 16 OR2 0 3 1 0 |POC:4|:1145
- 4 - C 19 OR2 0 3 1 0 |POC:4|:1154
- 7 - C 19 OR2 0 3 1 0 |POC:4|:1163
- 1 - C 04 OR2 0 3 1 0 |POC:4|:1172
- 6 - C 19 OR2 0 3 1 0 |POC:4|:1181
- 4 - C 23 OR2 0 3 1 0 |POC:4|:1190
- 3 - C 05 OR2 0 3 1 0 |POC:4|:1199
- 8 - C 05 AND2 ! 0 1 1 3 |POC:4|:1210
- 2 - C 04 OR2 ! 0 2 1 0 |POC:4|:1258
- 7 - C 05 DFFE + 0 3 1 3 |PRTSIM:3|:1
- 4 - C 05 DFFE + 1 3 0 1 |PRTSIM:3|COUNT1 (|PRTSIM:3|:6)
- 2 - C 05 DFFE + 1 2 0 2 |PRTSIM:3|COUNT0 (|PRTSIM:3|:7)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\yuhui\poc\poc\poctest.rpt
poctest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 20/ 96( 20%) 3/ 48( 6%) 8/ 48( 16%) 0/16( 0%) 1/16( 6%) 8/16( 50%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\yuhui\poc\poc\poctest.rpt
poctest
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 21 CLK
Device-Specific Information: d:\yuhui\poc\poc\poctest.rpt
poctest
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 RESET
LCELL 4 |POC:4|:1210
Device-Specific Information: d:\yuhui\poc\poc\poctest.rpt
poctest
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
RESET : INPUT;
RW : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(_LC1_C5, !_LC1_C23);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC3_C23, !_LC1_C23);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(_LC7_C15, !_LC1_C23);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(_LC3_C15, !_LC1_C23);
-- Node name is 'D4'
-- Equation name is 'D4', type is bidir
D4 = TRI(_LC5_C19, !_LC1_C23);
-- Node name is 'D5'
-- Equation name is 'D5', type is bidir
D5 = TRI(_LC1_C21, !_LC1_C23);
-- Node name is 'D6'
-- Equation name is 'D6', type is bidir
D6 = TRI(_LC4_C16, !_LC1_C23);
-- Node name is 'D7'
-- Equation name is 'D7', type is bidir
D7 = TRI(_LC8_C4, !_LC1_C23);
-- Node name is 'IRQ'
-- Equation name is 'IRQ', type is output
IRQ = !_LC2_C4;
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = _LC3_C5;
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = _LC4_C23;
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = _LC6_C19;
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = _LC1_C4;
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = _LC7_C19;
-- Node name is 'PD5'
-- Equation name is 'PD5', type is output
PD5 = _LC4_C19;
-- Node name is 'PD6'
-- Equation name is 'PD6', type is output
PD6 = _LC1_C16;
-- Node name is 'PD7'
-- Equation name is 'PD7', type is output
PD7 = _LC7_C16;
-- Node name is 'RDY'
-- Equation name is 'RDY', type is output
RDY = _LC7_C5;
-- Node name is 'TR'
-- Equation name is 'TR', type is output
TR = _LC8_C5;
-- Node name is '|POC:4|:46' = '|POC:4|BR0'
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = DFFE( _EQ001, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ001 = D0 & !_LC7_C23
# _LC6_C5 & _LC7_C23;
-- Node name is '|POC:4|:45' = '|POC:4|BR1'
-- Equation name is '_LC8_C23', type is buried
_LC8_C23 = DFFE( _EQ002, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ002 = D1 & !_LC7_C23
# _LC7_C23 & _LC8_C23;
-- Node name is '|POC:4|:44' = '|POC:4|BR2'
-- Equation name is '_LC8_C15', type is buried
_LC8_C15 = DFFE( _EQ003, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ003 = D2 & !_LC7_C23
# _LC7_C23 & _LC8_C15;
-- Node name is '|POC:4|:43' = '|POC:4|BR3'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = DFFE( _EQ004, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ004 = D3 & !_LC7_C23
# _LC5_C15 & _LC7_C23;
-- Node name is '|POC:4|:42' = '|POC:4|BR4'
-- Equation name is '_LC8_C19', type is buried
_LC8_C19 = DFFE( _EQ005, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ005 = D4 & !_LC7_C23
# _LC7_C23 & _LC8_C19;
-- Node name is '|POC:4|:41' = '|POC:4|BR5'
-- Equation name is '_LC1_C19', type is buried
_LC1_C19 = DFFE( _EQ006, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ006 = D5 & !_LC7_C23
# _LC1_C19 & _LC7_C23;
-- Node name is '|POC:4|:40' = '|POC:4|BR6'
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = DFFE( _EQ007, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ007 = D6 & !_LC7_C23
# _LC6_C16 & _LC7_C23;
-- Node name is '|POC:4|:39' = '|POC:4|BR7'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = DFFE( _EQ008, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ008 = D7 & !_LC7_C23
# _LC7_C23 & _LC8_C16;
-- Node name is '|POC:4|:28' = '|POC:4|CURRENT_STATE0'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = DFFE( _EQ009, GLOBAL(!CLK), GLOBAL( RESET), VCC, VCC);
_EQ009 = _LC3_C4 & !_LC4_C4 & !_LC6_C4
# !_LC3_C4 & !_LC6_C4 & _LC7_C5;
-- Node name is '|POC:4|:27' = '|POC:4|CURRENT_STATE1'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = DFFE( _EQ010, GLOBAL(!CLK), GLOBAL( RESET), VCC, VCC);
_EQ010 = _LC2_C21 & _LC3_C4 & !_LC6_C4 & RW;
-- Node name is '|POC:4|:38' = '|POC:4|SR0'
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = DFFE( _EQ011, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ011 = D0 & _LC3_C21 & RW
# _LC5_C4 & !RW
# !_LC3_C21 & _LC5_C4;
-- Node name is '|POC:4|:37' = '|POC:4|SR1'
-- Equation name is '_LC6_C23', type is buried
_LC6_C23 = DFFE( _EQ012, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ012 = D1 & _LC3_C21 & RW
# _LC6_C23 & !RW
# !_LC3_C21 & _LC6_C23;
-- Node name is '|POC:4|:36' = '|POC:4|SR2'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = DFFE( _EQ013, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ013 = D2 & _LC3_C21 & RW
# _LC2_C15 & !RW
# _LC2_C15 & !_LC3_C21;
-- Node name is '|POC:4|:35' = '|POC:4|SR3'
-- Equation name is '_LC6_C15', type is buried
_LC6_C15 = DFFE( _EQ014, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ014 = D3 & _LC3_C21 & RW
# _LC6_C15 & !RW
# !_LC3_C21 & _LC6_C15;
-- Node name is '|POC:4|:34' = '|POC:4|SR4'
-- Equation name is '_LC3_C19', type is buried
_LC3_C19 = DFFE( _EQ015, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ015 = D4 & _LC3_C21 & RW
# _LC3_C19 & !RW
# _LC3_C19 & !_LC3_C21;
-- Node name is '|POC:4|:33' = '|POC:4|SR5'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = DFFE( _EQ016, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ016 = D5 & _LC3_C21 & RW
# _LC4_C21 & !RW
# !_LC3_C21 & _LC4_C21;
-- Node name is '|POC:4|:32' = '|POC:4|SR6'
-- Equation name is '_LC5_C16', type is buried
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