poc.rpt

用VHDL编写的简单POC（并行输出控制）程序

-- Node name is ':32' = 'SR6' 
-- Equation name is 'SR6', location is LC4_A20, type is buried.
SR6      = DFFE( _EQ017, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ017 =  D6 &  _LC3_A19 &  RW
         # !RW &  SR6
         # !_LC3_A19 &  SR6;

-- Node name is ':31' = 'SR7' 
-- Equation name is 'SR7', location is LC8_A14, type is buried.
SR7      = DFFE( _EQ018, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ018 =  CURRENT_STATE0 & !CURRENT_STATE1;

-- Node name is 'TR' 
-- Equation name is 'TR', type is output 
TR       =  _LC1_A21;

-- Node name is '~128~1' 
-- Equation name is '~128~1', location is LC3_A19, type is buried.
-- synthesized logic cell 
_LC3_A19 = LCELL( _EQ019);
  _EQ019 = !A0 & !A1 & !A2 &  CS;

-- Node name is ':242' 
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ020);
  _EQ020 =  _LC3_A19 & !RW &  SR7
         #  _LC2_A20;

-- Node name is ':244' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ021);
  _EQ021 =  BR7 &  _LC2_A19 & !RW;

-- Node name is ':256' 
-- Equation name is '_LC1_A15', type is buried 
!_LC1_A15 = _LC1_A15~NOT;
_LC1_A15~NOT = LCELL( _EQ022);
  _EQ022 =  _LC3_A19 & !RW
         #  _LC2_A19 & !RW;

-- Node name is ':257' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ023);
  _EQ023 =  _LC3_A19 & !RW &  SR6
         #  _LC3_A20;

-- Node name is ':259' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ024);
  _EQ024 =  BR6 &  _LC2_A19 & !RW;

-- Node name is ':272' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ025);
  _EQ025 =  _LC3_A19 & !RW &  SR5
         #  _LC2_A22;

-- Node name is ':274' 
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = LCELL( _EQ026);
  _EQ026 =  BR5 &  _LC2_A19 & !RW;

-- Node name is ':287' 
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ027);
  _EQ027 =  _LC3_A19 & !RW &  SR4
         #  _LC3_A22;

-- Node name is ':289' 
-- Equation name is '_LC3_A22', type is buried 
_LC3_A22 = LCELL( _EQ028);
  _EQ028 =  BR4 &  _LC2_A19 & !RW;

-- Node name is ':302' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = LCELL( _EQ029);
  _EQ029 =  _LC3_A19 & !RW &  SR3
         #  _LC5_A18;

-- Node name is ':304' 
-- Equation name is '_LC5_A18', type is buried 
_LC5_A18 = LCELL( _EQ030);
  _EQ030 =  BR3 &  _LC2_A19 & !RW;

-- Node name is ':317' 
-- Equation name is '_LC4_A15', type is buried 
_LC4_A15 = LCELL( _EQ031);
  _EQ031 =  _LC3_A19 & !RW &  SR2
         #  _LC5_A15;

-- Node name is ':319' 
-- Equation name is '_LC5_A15', type is buried 
_LC5_A15 = LCELL( _EQ032);
  _EQ032 =  BR2 &  _LC2_A19 & !RW;

-- Node name is ':332' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ033);
  _EQ033 =  _LC3_A19 & !RW &  SR1
         #  _LC4_A19;

-- Node name is ':334' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ034);
  _EQ034 =  BR1 &  _LC2_A19 & !RW;

-- Node name is ':347' 
-- Equation name is '_LC4_A14', type is buried 
_LC4_A14 = LCELL( _EQ035);
  _EQ035 =  BR0 &  _LC2_A19 & !RW
         #  _LC3_A14;

-- Node name is ':348' 
-- Equation name is '_LC3_A14', type is buried 
_LC3_A14 = LCELL( _EQ036);
  _EQ036 =  _LC3_A19 & !RW &  SR0;

-- Node name is '~576~1' 
-- Equation name is '~576~1', location is LC4_A18, type is buried.
-- synthesized logic cell 
_LC4_A18 = LCELL( _EQ037);
  _EQ037 =  _LC3_A19
         # !RW
         # !_LC2_A19;

-- Node name is '~1044~1' 
-- Equation name is '~1044~1', location is LC2_A19, type is buried.
-- synthesized logic cell 
_LC2_A19 = LCELL( _EQ038);
  _EQ038 =  A0 & !A1 & !A2 &  CS;

-- Node name is ':1044' 
-- Equation name is '_LC1_A19', type is buried 
!_LC1_A19 = _LC1_A19~NOT;
_LC1_A19~NOT = LCELL( _EQ039);
  _EQ039 = !RW
         # !_LC2_A19;

-- Node name is ':1136' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ040);
  _EQ040 =  BR7 &  CURRENT_STATE1
         #  BR7 & !CURRENT_STATE0;

-- Node name is ':1145' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ041);
  _EQ041 =  BR6 &  CURRENT_STATE1
         #  BR6 & !CURRENT_STATE0;

-- Node name is ':1154' 
-- Equation name is '_LC1_A22', type is buried 
_LC1_A22 = LCELL( _EQ042);
  _EQ042 =  BR5 &  CURRENT_STATE1
         #  BR5 & !CURRENT_STATE0;

-- Node name is ':1163' 
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = LCELL( _EQ043);
  _EQ043 =  BR4 &  CURRENT_STATE1
         #  BR4 & !CURRENT_STATE0;

-- Node name is ':1172' 
-- Equation name is '_LC7_A18', type is buried 
_LC7_A18 = LCELL( _EQ044);
  _EQ044 =  BR3 &  CURRENT_STATE1
         #  BR3 & !CURRENT_STATE0;

-- Node name is ':1181' 
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = LCELL( _EQ045);
  _EQ045 =  BR2 &  CURRENT_STATE1
         #  BR2 & !CURRENT_STATE0;

-- Node name is ':1190' 
-- Equation name is '_LC1_A18', type is buried 
_LC1_A18 = LCELL( _EQ046);
  _EQ046 =  BR1 &  CURRENT_STATE1
         #  BR1 & !CURRENT_STATE0;

-- Node name is ':1199' 
-- Equation name is '_LC1_A14', type is buried 
_LC1_A14 = LCELL( _EQ047);
  _EQ047 =  BR0 &  CURRENT_STATE1
         #  BR0 & !CURRENT_STATE0;

-- Node name is ':1210' 
-- Equation name is '_LC1_A21', type is buried 
_LC1_A21 = LCELL( CURRENT_STATE1);

-- Node name is ':1258' 
-- Equation name is '_LC6_A14', type is buried 
!_LC6_A14 = _LC6_A14~NOT;
_LC6_A14~NOT = LCELL( _EQ048);
  _EQ048 = !SR0
         # !SR7;



Project Information                                   d:\yuhui\poc\poc\poc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,500K