📄 poc.rpt
字号:
- 3 - A 18 DFFE + 0 2 0 2 BR1 (:45)
- 5 - A 14 DFFE + 0 2 0 2 BR0 (:46)
- 3 - A 19 AND2 s 4 0 0 17 ~128~1
- 2 - A 14 OR2 1 3 1 0 :242
- 2 - A 20 AND2 1 2 0 1 :244
- 1 - A 15 OR2 ! 1 2 0 0 :256
- 1 - A 20 OR2 1 3 1 0 :257
- 3 - A 20 AND2 1 2 0 1 :259
- 8 - A 19 OR2 1 3 1 0 :272
- 2 - A 22 AND2 1 2 0 1 :274
- 8 - A 22 OR2 1 3 1 0 :287
- 3 - A 22 AND2 1 2 0 1 :289
- 2 - A 18 OR2 1 3 1 0 :302
- 5 - A 18 AND2 1 2 0 1 :304
- 4 - A 15 OR2 1 3 1 0 :317
- 5 - A 15 AND2 1 2 0 1 :319
- 5 - A 19 OR2 1 3 1 0 :332
- 4 - A 19 AND2 1 2 0 1 :334
- 4 - A 14 OR2 1 3 1 0 :347
- 3 - A 14 AND2 1 2 0 1 :348
- 4 - A 18 OR2 s 1 2 0 8 ~576~1
- 2 - A 19 AND2 s 4 0 0 12 ~1044~1
- 1 - A 19 OR2 ! 1 1 0 1 :1044
- 5 - A 20 OR2 0 3 1 0 :1136
- 6 - A 20 OR2 0 3 1 0 :1145
- 1 - A 22 OR2 0 3 1 0 :1154
- 6 - A 22 OR2 0 3 1 0 :1163
- 7 - A 18 OR2 0 3 1 0 :1172
- 6 - A 15 OR2 0 3 1 0 :1181
- 1 - A 18 OR2 0 3 1 0 :1190
- 1 - A 14 OR2 0 3 1 0 :1199
- 1 - A 21 AND2 0 1 1 0 :1210
- 6 - A 14 OR2 ! 0 2 1 0 :1258
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\yuhui\poc\poc\poc.rpt
poc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 15/ 96( 15%) 0/ 48( 0%) 16/ 48( 33%) 0/16( 0%) 2/16( 12%) 7/16( 43%)
B: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\yuhui\poc\poc\poc.rpt
poc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 CLK
Device-Specific Information: d:\yuhui\poc\poc\poc.rpt
poc
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 2 RESET
Device-Specific Information: d:\yuhui\poc\poc\poc.rpt
poc
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
RDY : INPUT;
RESET : INPUT;
RW : INPUT;
-- Node name is ':46' = 'BR0'
-- Equation name is 'BR0', location is LC5_A14, type is buried.
BR0 = DFFE( _EQ001, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ001 = D0 & !_LC4_A18
# BR0 & _LC4_A18;
-- Node name is ':45' = 'BR1'
-- Equation name is 'BR1', location is LC3_A18, type is buried.
BR1 = DFFE( _EQ002, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ002 = D1 & !_LC4_A18
# BR1 & _LC4_A18;
-- Node name is ':44' = 'BR2'
-- Equation name is 'BR2', location is LC8_A15, type is buried.
BR2 = DFFE( _EQ003, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ003 = D2 & !_LC4_A18
# BR2 & _LC4_A18;
-- Node name is ':43' = 'BR3'
-- Equation name is 'BR3', location is LC8_A18, type is buried.
BR3 = DFFE( _EQ004, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ004 = D3 & !_LC4_A18
# BR3 & _LC4_A18;
-- Node name is ':42' = 'BR4'
-- Equation name is 'BR4', location is LC5_A22, type is buried.
BR4 = DFFE( _EQ005, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ005 = D4 & !_LC4_A18
# BR4 & _LC4_A18;
-- Node name is ':41' = 'BR5'
-- Equation name is 'BR5', location is LC7_A22, type is buried.
BR5 = DFFE( _EQ006, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ006 = D5 & !_LC4_A18
# BR5 & _LC4_A18;
-- Node name is ':40' = 'BR6'
-- Equation name is 'BR6', location is LC7_A20, type is buried.
BR6 = DFFE( _EQ007, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ007 = D6 & !_LC4_A18
# BR6 & _LC4_A18;
-- Node name is ':39' = 'BR7'
-- Equation name is 'BR7', location is LC8_A20, type is buried.
BR7 = DFFE( _EQ008, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ008 = D7 & !_LC4_A18
# BR7 & _LC4_A18;
-- Node name is ':28' = 'CURRENT_STATE0'
-- Equation name is 'CURRENT_STATE0', location is LC2_A15, type is buried.
CURRENT_STATE0 = DFFE( _EQ009, GLOBAL(!CLK), GLOBAL( RESET), VCC, VCC);
_EQ009 = CURRENT_STATE0 & !CURRENT_STATE1 & !_LC1_A19
# !CURRENT_STATE0 & !CURRENT_STATE1 & RDY;
-- Node name is ':27' = 'CURRENT_STATE1'
-- Equation name is 'CURRENT_STATE1', location is LC3_A15, type is buried.
CURRENT_STATE1 = DFFE( _EQ010, GLOBAL(!CLK), GLOBAL( RESET), VCC, VCC);
_EQ010 = CURRENT_STATE0 & !CURRENT_STATE1 & _LC2_A19 & RW;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(_LC4_A14, !_LC1_A15);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC5_A19, !_LC1_A15);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(_LC4_A15, !_LC1_A15);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(_LC2_A18, !_LC1_A15);
-- Node name is 'D4'
-- Equation name is 'D4', type is bidir
D4 = TRI(_LC8_A22, !_LC1_A15);
-- Node name is 'D5'
-- Equation name is 'D5', type is bidir
D5 = TRI(_LC8_A19, !_LC1_A15);
-- Node name is 'D6'
-- Equation name is 'D6', type is bidir
D6 = TRI(_LC1_A20, !_LC1_A15);
-- Node name is 'D7'
-- Equation name is 'D7', type is bidir
D7 = TRI(_LC2_A14, !_LC1_A15);
-- Node name is 'IRQ'
-- Equation name is 'IRQ', type is output
IRQ = !_LC6_A14;
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = _LC1_A14;
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = _LC1_A18;
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = _LC6_A15;
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = _LC7_A18;
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = _LC6_A22;
-- Node name is 'PD5'
-- Equation name is 'PD5', type is output
PD5 = _LC1_A22;
-- Node name is 'PD6'
-- Equation name is 'PD6', type is output
PD6 = _LC6_A20;
-- Node name is 'PD7'
-- Equation name is 'PD7', type is output
PD7 = _LC5_A20;
-- Node name is ':38' = 'SR0'
-- Equation name is 'SR0', location is LC7_A14, type is buried.
SR0 = DFFE( _EQ011, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ011 = D0 & _LC3_A19 & RW
# !RW & SR0
# !_LC3_A19 & SR0;
-- Node name is ':37' = 'SR1'
-- Equation name is 'SR1', location is LC6_A19, type is buried.
SR1 = DFFE( _EQ012, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ012 = D1 & _LC3_A19 & RW
# !RW & SR1
# !_LC3_A19 & SR1;
-- Node name is ':36' = 'SR2'
-- Equation name is 'SR2', location is LC7_A15, type is buried.
SR2 = DFFE( _EQ013, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ013 = D2 & _LC3_A19 & RW
# !RW & SR2
# !_LC3_A19 & SR2;
-- Node name is ':35' = 'SR3'
-- Equation name is 'SR3', location is LC6_A18, type is buried.
SR3 = DFFE( _EQ014, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ014 = D3 & _LC3_A19 & RW
# !RW & SR3
# !_LC3_A19 & SR3;
-- Node name is ':34' = 'SR4'
-- Equation name is 'SR4', location is LC4_A22, type is buried.
SR4 = DFFE( _EQ015, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ015 = D4 & _LC3_A19 & RW
# !RW & SR4
# !_LC3_A19 & SR4;
-- Node name is ':33' = 'SR5'
-- Equation name is 'SR5', location is LC7_A19, type is buried.
SR5 = DFFE( _EQ016, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ016 = D5 & _LC3_A19 & RW
# !RW & SR5
# !_LC3_A19 & SR5;
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