print.vhd

用VHDL编写的简单POC（并行输出控制）程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PRINT IS
	PORT (RDY: BUFFER STD_LOGIC; TR, CLK, RESET: IN STD_LOGIC);
END PRINT;

ARCHITECTURE BEHAVIOR OF PRINT IS
	SIGNAL COUNT: INTEGER RANGE 0 TO 7;
    TYPE   STATE_TYPE  IS(WAITING,PRINTING);
    SIGNAL  PRINT:STATE_TYPE;
BEGIN
  
	PROCESS(CLK, RESET)
	BEGIN
	IF RESET = '1' THEN
		PRINT<=WAITING;
   ELSIF RISING_EDGE(CLK) THEN

CASE   PRINT   IS
WHEN  WAITING=>
		COUNT <= 0;
        RDY<='1';
      IF  TR='1'   THEN  
        PRINT<=PRINTING;
        RDY<='0';
        END  IF;
WHEN  PRINTING=>
      IF COUNT = 7 THEN
                COUNT<=0;
				RDY <= '1';
                PRINT<=WAITING;
		ELSIF RDY = '0' THEN
				COUNT <= COUNT + 1;
		END IF;

END  CASE;
	END IF;
	END PROCESS;
END BEHAVIOR;