📄 print3.rpt
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p = Packed register
Device-Specific Information: d:\yuhui\print3.rpt
print3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 0/ 48( 0%) 7/ 48( 14%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\yuhui\print3.rpt
print3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 CLK
Device-Specific Information: d:\yuhui\print3.rpt
print3
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 2 RESET
Device-Specific Information: d:\yuhui\print3.rpt
print3
** EQUATIONS **
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
CLK : INPUT;
RESET : INPUT;
TR : INPUT;
-- Node name is ':31' = 'COUNT0'
-- Equation name is 'COUNT0', location is LC6_B14, type is buried.
COUNT0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ001 = COUNT0 & _LC2_B14 & _LC4_B14
# !COUNT0 & !_LC2_B14 & _LC4_B14;
-- Node name is ':30' = 'COUNT1'
-- Equation name is 'COUNT1', location is LC5_B14, type is buried.
COUNT1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ002 = _LC3_B14 & _LC4_B14;
-- Node name is 'D10'
-- Equation name is 'D10', type is output
D10 = _LC2_B16;
-- Node name is 'D11'
-- Equation name is 'D11', type is output
D11 = _LC8_B16;
-- Node name is 'D12'
-- Equation name is 'D12', type is output
D12 = _LC1_B16;
-- Node name is 'D13'
-- Equation name is 'D13', type is output
D13 = _LC6_B16;
-- Node name is 'D14'
-- Equation name is 'D14', type is output
D14 = _LC7_B16;
-- Node name is 'D15'
-- Equation name is 'D15', type is output
D15 = _LC4_B16;
-- Node name is 'D16'
-- Equation name is 'D16', type is output
D16 = _LC3_B16;
-- Node name is 'D17'
-- Equation name is 'D17', type is output
D17 = _LC5_B16;
-- Node name is 'PRINT~1'
-- Equation name is 'PRINT~1', location is LC7_B14, type is buried.
PRINT~1 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ003 = !COUNT1 & PRINT~1
# !COUNT0 & PRINT~1
# !PRINT~1 & TR;
-- Node name is 'RDY'
-- Equation name is 'RDY', type is output
RDY = _LC2_B14;
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC1_B21, type is buried.
-- synthesized logic cell
!_LC1_B21 = _LC1_B21~NOT;
_LC1_B21~NOT = LCELL(!RESET);
-- Node name is ':1'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ004 = _LC8_B14 & PRINT~1
# !PRINT~1 & !TR;
-- Node name is ':14'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ005 = B7 & !_LC1_B14
# _LC1_B14 & _LC5_B16;
-- Node name is ':16'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ006 = B6 & !_LC1_B14
# _LC1_B14 & _LC3_B16;
-- Node name is ':18'
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ007 = B5 & !_LC1_B14
# _LC1_B14 & _LC4_B16;
-- Node name is ':20'
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ008 = B4 & !_LC1_B14
# _LC1_B14 & _LC7_B16;
-- Node name is ':22'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ009 = B3 & !_LC1_B14
# _LC1_B14 & _LC6_B16;
-- Node name is ':24'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = DFFE( _EQ010, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ010 = B2 & !_LC1_B14
# _LC1_B14 & _LC1_B16;
-- Node name is ':26'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = DFFE( _EQ011, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ011 = B1 & !_LC1_B14
# _LC1_B14 & _LC8_B16;
-- Node name is ':28'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = DFFE( _EQ012, GLOBAL( CLK), VCC, VCC, !_LC1_B21);
_EQ012 = B0 & !_LC1_B14
# _LC1_B14 & _LC2_B16;
-- Node name is ':234'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ013);
_EQ013 = !COUNT0 & COUNT1
# COUNT0 & !COUNT1 & !_LC2_B14
# COUNT1 & _LC2_B14;
-- Node name is ':255'
-- Equation name is '_LC8_B14', type is buried
_LC8_B14 = LCELL( _EQ014);
_EQ014 = _LC2_B14
# COUNT0 & COUNT1;
-- Node name is '~332~1'
-- Equation name is '~332~1', location is LC1_B14, type is buried.
-- synthesized logic cell
_LC1_B14 = LCELL( _EQ015);
_EQ015 = !COUNT1
# !COUNT0
# !PRINT~1;
-- Node name is ':359'
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ016);
_EQ016 = !COUNT1 & PRINT~1
# !COUNT0 & PRINT~1;
Project Information d:\yuhui\print3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,602K
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