poc3.vhd

用VHDL编写的简单POC（并行输出控制）程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity  POC3  is
port(RW,CS,RDY,CLK,RESET:  IN  STD_LOGIC;
   	 IRQ,TR:  OUT   STD_LOGIC;
     A: IN  STD_LOGIC_VECTOR(2  DOWNTO  0);
     D: INOUT  STD_LOGIC_VECTOR(7 DOWNTO  0);
     PD:OUT   STD_LOGIC_VECTOR(7  DOWNTO  0)
     );
 end   POC3;
ARCHITECTURE   BEHAVE   OF   POC3 IS
SIGNAL BR,SR: STD_LOGIC_VECTOR(7 DOWNTO 0);
type   STATE is(Q0,Q1,Q2);            -- Q0--WAITPRT,Q1--WAITDATA,Q2--RESPONSE;
SIGNAL CURRENT_STATE,NEXT_STATE:  STATE:=Q1;
BEGIN


PROCESS(CLK,RESET)
BEGIN
IF   RESET ='1'   THEN
			CURRENT_STATE <= Q1;
ELSIF (CLK'EVENT AND CLK='0') THEN
			CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS;

IRQ <= '0' WHEN SR(7) = '1' AND SR(0) = '1' ELSE '1';


PROCESS(CS,RW,A,CURRENT_STATE,SR,BR,CLK)
begin
      IF FALLING_EDGE(CLK) THEN

		IF CS = '1' AND RW = '1' AND A = "000" THEN
			SR <= D;
		ELSIF CS = '1' AND RW = '1' AND A = "001" THEN
			BR <= D;
		END IF;
		END   IF;
      IF CS = '1' AND RW = '0' AND A = "000" THEN
			D <= SR;
		ELSIF CS = '1' AND RW = '0' AND A = "001" THEN
			D <= BR;
		ELSE
			D <= "ZZZZZZZZ";
		END IF;
CASE   CURRENT_STATE   IS
WHEN   Q1=>  SR(7)<='1';
WHEN   OTHERS=> SR(7)<='0';
END  CASE;
END   PROCESS;



PROCESS( CURRENT_STATE,RDY, CS, RW, A, BR)
   BEGIN
	CASE CURRENT_STATE IS
		WHEN Q0 =>
			PD <= BR;
			TR<='0';
			IF RDY = '1' THEN
				NEXT_STATE <= Q1;
                
			ELSE
				NEXT_STATE <= Q0;
			END IF;
		WHEN Q1=>
			PD <= "ZZZZZZZZ";
  			TR <= '0';
			IF CS = '1' AND RW = '1' AND A = "001" THEN
				NEXT_STATE <= Q2;
			ELSE
				NEXT_STATE <= Q1;
			END IF;
		WHEN Q2 =>
			TR <= '1';
			PD <= BR;
			NEXT_STATE <= Q0;
		END CASE;
	END PROCESS;
		 
END   BEHAVE;