systerm.rpt

用VHDL编写的简单POC（并行输出控制）程序

  _EQ012 =  D1 &  _LC2_C16 &  RW
         #  _LC6_A13 & !RW
         # !_LC2_C16 &  _LC6_A13;

-- Node name is '|POC3:1|:36' = '|POC3:1|SR2' 
-- Equation name is '_LC4_B17', type is buried 
_LC4_B17 = DFFE( _EQ013, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ013 =  D2 &  _LC2_C16 &  RW
         #  _LC4_B17 & !RW
         # !_LC2_C16 &  _LC4_B17;

-- Node name is '|POC3:1|:35' = '|POC3:1|SR3' 
-- Equation name is '_LC8_B17', type is buried 
_LC8_B17 = DFFE( _EQ014, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ014 =  D3 &  _LC2_C16 &  RW
         #  _LC8_B17 & !RW
         # !_LC2_C16 &  _LC8_B17;

-- Node name is '|POC3:1|:34' = '|POC3:1|SR4' 
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = DFFE( _EQ015, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ015 =  D4 &  _LC2_C16 &  RW
         #  _LC4_C22 & !RW
         # !_LC2_C16 &  _LC4_C22;

-- Node name is '|POC3:1|:33' = '|POC3:1|SR5' 
-- Equation name is '_LC8_C22', type is buried 
_LC8_C22 = DFFE( _EQ016, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ016 =  D5 &  _LC2_C16 &  RW
         #  _LC8_C22 & !RW
         # !_LC2_C16 &  _LC8_C22;

-- Node name is '|POC3:1|:32' = '|POC3:1|SR6' 
-- Equation name is '_LC7_C16', type is buried 
_LC7_C16 = DFFE( _EQ017, GLOBAL(!CLK),  VCC,  VCC,  VCC);
  _EQ017 =  D6 &  _LC2_C16 &  RW
         #  _LC7_C16 & !RW
         # !_LC2_C16 &  _LC7_C16;

-- Node name is '|POC3:1|~326~1' 
-- Equation name is '_LC7_A13', type is buried 
-- synthesized logic cell 
_LC7_A13 = LCELL( _EQ018);
  _EQ018 =  _LC2_C16
         # !RW
         # !_LC4_C16;

-- Node name is '|POC3:1|~530~1' 
-- Equation name is '_LC2_C16', type is buried 
-- synthesized logic cell 
_LC2_C16 = LCELL( _EQ019);
  _EQ019 = !A0 & !A1 & !A2 &  CS;

-- Node name is '|POC3:1|:644' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = LCELL( _EQ020);
  _EQ020 =  _LC2_C16 &  _LC4_A20 & !RW
         #  _LC8_C16;

-- Node name is '|POC3:1|:646' 
-- Equation name is '_LC8_C16', type is buried 
_LC8_C16 = LCELL( _EQ021);
  _EQ021 =  _LC4_C16 &  _LC7_C23 & !RW;

-- Node name is '|POC3:1|:658' 
-- Equation name is '_LC1_A13', type is buried 
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL( _EQ022);
  _EQ022 =  _LC2_C16 & !RW
         #  _LC4_C16 & !RW;

-- Node name is '|POC3:1|:659' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = LCELL( _EQ023);
  _EQ023 =  _LC2_C16 &  _LC7_C16 & !RW
         #  _LC5_C16;

-- Node name is '|POC3:1|:661' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = LCELL( _EQ024);
  _EQ024 =  _LC4_C16 &  _LC6_C16 & !RW;

-- Node name is '|POC3:1|:674' 
-- Equation name is '_LC5_C22', type is buried 
_LC5_C22 = LCELL( _EQ025);
  _EQ025 =  _LC2_C16 &  _LC8_C22 & !RW
         #  _LC7_C22;

-- Node name is '|POC3:1|:676' 
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = LCELL( _EQ026);
  _EQ026 =  _LC4_C16 &  _LC6_C22 & !RW;

-- Node name is '|POC3:1|:689' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ027);
  _EQ027 =  _LC2_C16 &  _LC4_C22 & !RW
         #  _LC3_C22;

-- Node name is '|POC3:1|:691' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ028);
  _EQ028 =  _LC1_C22 &  _LC4_C16 & !RW;

-- Node name is '|POC3:1|:704' 
-- Equation name is '_LC1_B17', type is buried 
_LC1_B17 = LCELL( _EQ029);
  _EQ029 =  _LC2_C16 &  _LC8_B17 & !RW
         #  _LC6_B17;

-- Node name is '|POC3:1|:706' 
-- Equation name is '_LC6_B17', type is buried 
_LC6_B17 = LCELL( _EQ030);
  _EQ030 =  _LC4_C16 &  _LC5_B17 & !RW;

-- Node name is '|POC3:1|:719' 
-- Equation name is '_LC7_B17', type is buried 
_LC7_B17 = LCELL( _EQ031);
  _EQ031 =  _LC2_C16 &  _LC4_B17 & !RW
         #  _LC2_B17;

-- Node name is '|POC3:1|:721' 
-- Equation name is '_LC2_B17', type is buried 
_LC2_B17 = LCELL( _EQ032);
  _EQ032 =  _LC3_B17 &  _LC4_C16 & !RW;

-- Node name is '|POC3:1|:734' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = LCELL( _EQ033);
  _EQ033 =  _LC2_C16 &  _LC6_A13 & !RW
         #  _LC2_A13;

-- Node name is '|POC3:1|:736' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ034);
  _EQ034 =  _LC4_A13 &  _LC4_C16 & !RW;

-- Node name is '|POC3:1|:749' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ035);
  _EQ035 =  _LC4_C16 &  _LC8_A13 & !RW
         #  _LC1_A20;

-- Node name is '|POC3:1|:750' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ036);
  _EQ036 =  _LC2_C16 &  _LC7_A20 & !RW;

-- Node name is '|POC3:1|~1043~1' 
-- Equation name is '_LC4_C16', type is buried 
-- synthesized logic cell 
_LC4_C16 = LCELL( _EQ037);
  _EQ037 =  A0 & !A1 & !A2 &  CS;

-- Node name is '|POC3:1|:1043' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ038);
  _EQ038 =  _LC4_C16 &  RW;

-- Node name is '|POC3:1|:1127' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ039);
  _EQ039 =  _LC3_A20 & !_LC8_A20;

-- Node name is '|POC3:1|:1257' 
-- Equation name is '_LC6_A20', type is buried 
!_LC6_A20 = _LC6_A20~NOT;
_LC6_A20~NOT = LCELL(!_LC8_A20);

-- Node name is '|POC3:1|:1305' 
-- Equation name is '_LC5_A20', type is buried 
!_LC5_A20 = _LC5_A20~NOT;
_LC5_A20~NOT = LCELL( _EQ040);
  _EQ040 =  _LC8_A20
         # !_LC3_A20
         # !_LC7_A20;

-- Node name is '|PRINT:12|:7' = '|PRINT:12|COUNT0' 
-- Equation name is '_LC3_A16', type is buried 
_LC3_A16 = DFFE( _EQ041, GLOBAL( CLK), !_LC6_A20,  VCC, !_LC2_A16);
  _EQ041 =  _LC1_A16 &  _LC3_A16
         # !_LC1_A16 & !_LC3_A16;

-- Node name is '|PRINT:12|:6' = '|PRINT:12|COUNT1' 
-- Equation name is '_LC4_A16', type is buried 
_LC4_A16 = DFFE( _EQ042, GLOBAL( CLK), !_LC6_A20,  VCC, !_LC2_A16);
  _EQ042 = !_LC3_A16 &  _LC4_A16
         # !_LC1_A16 &  _LC3_A16 & !_LC4_A16
         #  _LC1_A16 &  _LC4_A16;

-- Node name is '|PRINT:12|:1' 
-- Equation name is '_LC1_A16', type is buried 
_LC1_A16 = DFFE( _EQ043, GLOBAL( CLK), !_LC6_A20, GLOBAL(!RESET),  VCC);
  _EQ043 =  _LC1_A16
         #  _LC3_A16 &  _LC4_A16;



Project Information                                       d:\yuhui\systerm.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,629K