poc4.vhd

用VHDL编写的简单POC（并行输出控制）程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity  POC4  is
port(RW,CS,RDY,CLK,RESET:  IN  STD_LOGIC;
   	 IRQ,TR:  OUT   STD_LOGIC;
     A: IN  STD_LOGIC_VECTOR(2  DOWNTO  0);
     D: INOUT  STD_LOGIC_VECTOR(7 DOWNTO  0);
     PD:OUT   STD_LOGIC_VECTOR(7  DOWNTO  0)
     );
 end   POC4;
ARCHITECTURE   BEHAVE   OF   POC4 IS
SIGNAL BR,SR: STD_LOGIC_VECTOR(7 DOWNTO 0);
type   STATE is(PRINT,WAITDATA,WAITPRT);            
SIGNAL CURRENT_STATE,NEXT_STATE:  STATE:=WAITDATA;
BEGIN


PROCESS(CLK,RESET)
BEGIN
IF   RESET ='1'   THEN
			CURRENT_STATE <= WAITDATA;
ELSIF (CLK'EVENT AND CLK='1') THEN
			CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS;

IRQ <= '0' WHEN SR(7) = '1' AND SR(0) = '1' ELSE '1';





PROCESS( CURRENT_STATE,RDY, CS, RW, A, BR,SR,CLK)
   BEGIN
 IF CLK'EVENT AND CLK='1' THEN

		IF CS = '1' AND RW = '1' AND A = "000" THEN
			SR <= D;
		ELSIF CS = '1' AND RW = '1' AND A = "001" THEN
			BR <= D;
		END IF;
		END   IF;
      IF CS = '1' AND RW = '0' AND A = "000" THEN
			D <= SR;
		ELSIF CS = '1' AND RW = '0' AND A = "001" THEN
			D <= BR;
		ELSE
			D <= "ZZZZZZZZ";
		END IF;

	CASE CURRENT_STATE IS
		WHEN PRINT =>
            SR(7)<='0';

			PD <= BR;
			TR<='0';
			IF RDY = '1' THEN
				NEXT_STATE <= WAITDATA;
                
			ELSE
				NEXT_STATE <= PRINT;
			END IF;
		WHEN WAITDATA=>
            SR(7)<='1';

			PD <= "ZZZZZZZZ";
  			TR <= '0';
			IF CS = '1' AND RW = '1' AND A = "001" THEN
				NEXT_STATE <= WAITPRT;
                 ELSE
				NEXT_STATE <= WAITDATA;
			END IF;
		WHEN WAITPRT =>
             SR(7)<='0';

			TR <= '1';
			PD <= BR;
    IF   RDY='1'    THEN
			NEXT_STATE <= PRINT;
      ELSE    
            NEXT_STATE<=WAITPRT;
      END  IF;
		END CASE;


	END PROCESS;
		 
END   BEHAVE;