poc5.vhd

用VHDL编写的简单POC（并行输出控制）程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY   POC5 IS
PORT(RW,CS,RDY,CLK,RESET:  IN  STD_LOGIC;
   	 IRQ,TR:  OUT   STD_LOGIC;
     A: IN  STD_LOGIC_VECTOR(2  DOWNTO  0);
     D: INOUT  STD_LOGIC_VECTOR(7 DOWNTO  0);
     PD:OUT   STD_LOGIC_VECTOR(7  DOWNTO  0)
     );
 end   POC5;
ARCHITECTURE   BEHAVE   OF   POC5 IS
SIGNAL BR,SR: STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE   STATE IS(WAITDATA,WAITPRT,RESPONSE);            -- Q0--WAITPRT,Q1--WAITDATA,Q2--RESPONSE;
SIGNAL CURRENT_STATE,NEXT_STATE:  STATE;
BEGIN
IRQ <= '0' WHEN SR(7) = '1' AND SR(0) = '1' ELSE '1';


PROCESS(CLK,RESET)
BEGIN
IF   RESET ='1'   THEN
			CURRENT_STATE <= WAITDATA;
ELSIF (CLK'EVENT AND CLK='0') THEN
			CURRENT_STATE <= NEXT_STATE;
END IF;
END PROCESS;



PROCESS(CS,RW,A,CURRENT_STATE,SR,BR,CLK)
begin
      IF FALLING_EDGE(CLK) THEN

		IF CS = '1' AND RW = '1' AND A = "000" THEN
			SR <= D;
		ELSIF CS = '1' AND RW = '1' AND A = "001" THEN
			BR <= D;
		END IF;
		END   IF;
   IF CS = '1' AND RW = '0' AND A = "000" THEN
				D <= SR;
		ELSIF CS = '1' AND RW = '0' AND A = "001" THEN
			D <= BR;
		ELSE
		D <= "ZZZZZZZZ";
		END IF;
CASE   CURRENT_STATE   IS
WHEN   WAITDATA=>  SR(7)<='1';
WHEN   OTHERS=> SR(7)<='0';
END  CASE;
END   PROCESS;



PROCESS( CURRENT_STATE,RDY, CS, RW, A, BR)
   BEGIN
	CASE CURRENT_STATE IS
       WHEN WAITDATA=>
			PD <= "ZZZZZZZZ";
  			TR <= '0';
			IF CS = '1' AND RW = '1' AND A = "001" THEN
				NEXT_STATE <= WAITPRT;
 				TR<='1';
			ELSE
				NEXT_STATE <= WAITDATA;
			END IF;

		WHEN WAITPRT=>
		IF RDY = '1' THEN
				NEXT_STATE <=RESPONSE;
                PD <= BR;
			ELSE
				NEXT_STATE <= WAITPRT;
			END IF;
		WHEN OTHERS =>
			     TR <= '0';
        IF    RDY='0'   THEN
			NEXT_STATE <= WAITDATA;
        END  IF;
		END CASE;
	END PROCESS;
		 
END   BEHAVE;