📄 print2.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\study\yuhui\print2.rpt
print2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 03 DFFE + 1 2 0 2 PRINT~1
- 1 - C 03 SOFT s ! 1 0 0 3 RESET~1
- 5 - C 03 DFFE + 1 3 1 3 :1
- 6 - C 03 DFFE + 0 3 0 4 COUNT1 (:6)
- 3 - C 03 DFFE + 0 3 0 4 COUNT0 (:7)
- 4 - C 03 OR2 0 3 0 1 :103
- 8 - C 03 OR2 0 3 0 1 :127
- 2 - C 03 OR2 0 3 0 2 :175
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\study\yuhui\print2.rpt
print2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\study\yuhui\print2.rpt
print2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CLK
Device-Specific Information: d:\study\yuhui\print2.rpt
print2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 2 RESET
Device-Specific Information: d:\study\yuhui\print2.rpt
print2
** EQUATIONS **
CLK : INPUT;
RESET : INPUT;
TR : INPUT;
-- Node name is ':7' = 'COUNT0'
-- Equation name is 'COUNT0', location is LC3_C3, type is buried.
COUNT0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, !_LC1_C3);
_EQ001 = COUNT0 & _LC2_C3 & _LC5_C3
# !COUNT0 & _LC2_C3 & !_LC5_C3;
-- Node name is ':6' = 'COUNT1'
-- Equation name is 'COUNT1', location is LC6_C3, type is buried.
COUNT1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, !_LC1_C3);
_EQ002 = _LC2_C3 & _LC4_C3;
-- Node name is 'PRINT~1'
-- Equation name is 'PRINT~1', location is LC7_C3, type is buried.
PRINT~1 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ003 = !COUNT1 & PRINT~1
# !COUNT0 & PRINT~1
# !PRINT~1 & TR;
-- Node name is 'RDY'
-- Equation name is 'RDY', type is output
RDY = _LC5_C3;
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC1_C3, type is buried.
-- synthesized logic cell
!_LC1_C3 = _LC1_C3~NOT;
_LC1_C3~NOT = LCELL(!RESET);
-- Node name is ':1'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, !_LC1_C3);
_EQ004 = _LC8_C3 & PRINT~1
# !PRINT~1 & !TR;
-- Node name is ':103'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = LCELL( _EQ005);
_EQ005 = !COUNT0 & COUNT1
# COUNT0 & !COUNT1 & !_LC5_C3
# COUNT1 & _LC5_C3;
-- Node name is ':127'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = LCELL( _EQ006);
_EQ006 = _LC5_C3
# COUNT0 & COUNT1;
-- Node name is ':175'
-- Equation name is '_LC2_C3', type is buried
_LC2_C3 = LCELL( _EQ007);
_EQ007 = !COUNT1 & PRINT~1
# !COUNT0 & PRINT~1;
Project Information d:\study\yuhui\print2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,493K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -