poc.rpt

用VHDL编写的简单POC（并行输出控制）程序

SR1      = DFFE( _EQ012, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ012 =  D1 &  _LC8_C22 &  RW
         # !RW &  SR1
         # !_LC8_C22 &  SR1;

-- Node name is ':36' = 'SR2' 
-- Equation name is 'SR2', location is LC4_C19, type is buried.
SR2      = DFFE( _EQ013, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ013 =  D2 &  _LC8_C22 &  RW
         # !RW &  SR2
         # !_LC8_C22 &  SR2;

-- Node name is ':35' = 'SR3' 
-- Equation name is 'SR3', location is LC8_C19, type is buried.
SR3      = DFFE( _EQ014, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ014 =  D3 &  _LC8_C22 &  RW
         # !RW &  SR3
         # !_LC8_C22 &  SR3;

-- Node name is ':34' = 'SR4' 
-- Equation name is 'SR4', location is LC5_A20, type is buried.
SR4      = DFFE( _EQ015, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ015 =  D4 &  _LC8_C22 &  RW
         # !RW &  SR4
         # !_LC8_C22 &  SR4;

-- Node name is ':33' = 'SR5' 
-- Equation name is 'SR5', location is LC8_A20, type is buried.
SR5      = DFFE( _EQ016, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ016 =  D5 &  _LC8_C22 &  RW
         # !RW &  SR5
         # !_LC8_C22 &  SR5;

-- Node name is ':32' = 'SR6' 
-- Equation name is 'SR6', location is LC5_C22, type is buried.
SR6      = DFFE( _EQ017, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ017 =  D6 &  _LC8_C22 &  RW
         # !RW &  SR6
         # !_LC8_C22 &  SR6;

-- Node name is 'TR' 
-- Equation name is 'TR', type is output 
TR       =  _LC5_A23;

-- Node name is '~373~1' 
-- Equation name is '~373~1', location is LC3_A18, type is buried.
-- synthesized logic cell 
_LC3_A18 = LCELL( _EQ018);
  _EQ018 =  _LC8_C22
         # !RW
         # !_LC6_C22;

-- Node name is '~577~1' 
-- Equation name is '~577~1', location is LC8_C22, type is buried.
-- synthesized logic cell 
_LC8_C22 = LCELL( _EQ019);
  _EQ019 = !A0 & !A1 & !A2 &  CS;

-- Node name is ':691' 
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = LCELL( _EQ020);
  _EQ020 =  _LC1_A23 &  _LC8_C22 & !RW
         #  _LC7_C22;

-- Node name is ':693' 
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = LCELL( _EQ021);
  _EQ021 =  BR7 &  _LC6_C22 & !RW;

-- Node name is ':705' 
-- Equation name is '_LC4_A18', type is buried 
!_LC4_A18 = _LC4_A18~NOT;
_LC4_A18~NOT = LCELL( _EQ022);
  _EQ022 =  _LC8_C22 & !RW
         #  _LC6_C22 & !RW;

-- Node name is ':706' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ023);
  _EQ023 =  _LC8_C22 & !RW &  SR6
         #  _LC3_C22;

-- Node name is ':708' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ024);
  _EQ024 =  BR6 &  _LC6_C22 & !RW;

-- Node name is ':721' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ025);
  _EQ025 =  _LC8_C22 & !RW &  SR5
         #  _LC7_A20;

-- Node name is ':723' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ026);
  _EQ026 =  BR5 &  _LC6_C22 & !RW;

-- Node name is ':736' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ027);
  _EQ027 =  _LC8_C22 & !RW &  SR4
         #  _LC3_A20;

-- Node name is ':738' 
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ028);
  _EQ028 =  BR4 &  _LC6_C22 & !RW;

-- Node name is ':751' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ029);
  _EQ029 =  _LC8_C22 & !RW &  SR3
         #  _LC6_C19;

-- Node name is ':753' 
-- Equation name is '_LC6_C19', type is buried 
_LC6_C19 = LCELL( _EQ030);
  _EQ030 =  BR3 &  _LC6_C22 & !RW;

-- Node name is ':766' 
-- Equation name is '_LC7_C19', type is buried 
_LC7_C19 = LCELL( _EQ031);
  _EQ031 =  _LC8_C22 & !RW &  SR2
         #  _LC2_C19;

-- Node name is ':768' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ032);
  _EQ032 =  BR2 &  _LC6_C22 & !RW;

-- Node name is ':781' 
-- Equation name is '_LC7_A18', type is buried 
_LC7_A18 = LCELL( _EQ033);
  _EQ033 =  _LC8_C22 & !RW &  SR1
         #  _LC2_A18;

-- Node name is ':783' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = LCELL( _EQ034);
  _EQ034 =  BR1 &  _LC6_C22 & !RW;

-- Node name is ':796' 
-- Equation name is '_LC6_A18', type is buried 
_LC6_A18 = LCELL( _EQ035);
  _EQ035 =  BR0 &  _LC6_C22 & !RW
         #  _LC2_A23;

-- Node name is ':797' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ036);
  _EQ036 =  _LC8_C22 & !RW &  SR0;

-- Node name is '~983~1' 
-- Equation name is '~983~1', location is LC6_C22, type is buried.
-- synthesized logic cell 
_LC6_C22 = LCELL( _EQ037);
  _EQ037 =  A0 & !A1 & !A2 &  CS;

-- Node name is ':983' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = LCELL( _EQ038);
  _EQ038 =  _LC6_C22 &  RW;

-- Node name is ':1147' 
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = LCELL( _EQ039);
  _EQ039 =  CURRENT_STATE0 & !CURRENT_STATE1;

-- Node name is ':1296' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( CURRENT_STATE1);

-- Node name is ':1384' 
-- Equation name is '_LC3_A23', type is buried 
!_LC3_A23 = _LC3_A23~NOT;
_LC3_A23~NOT = LCELL( _EQ040);
  _EQ040 =  CURRENT_STATE1
         # !CURRENT_STATE0
         # !SR0;



Project Information                                        d:\study\kb\poc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,330K