📄 poc.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 23 DFFE + 1 2 0 4 CURRENT_STATE1 (:27)
- 6 - A 23 DFFE + ! 1 2 0 3 CURRENT_STATE0 (:28)
- 5 - C 22 DFFE + 1 2 0 1 SR6 (:32)
- 8 - A 20 DFFE + 1 2 0 1 SR5 (:33)
- 5 - A 20 DFFE + 1 2 0 1 SR4 (:34)
- 8 - C 19 DFFE + 1 2 0 1 SR3 (:35)
- 4 - C 19 DFFE + 1 2 0 1 SR2 (:36)
- 5 - A 18 DFFE + 1 2 0 1 SR1 (:37)
- 7 - A 23 DFFE + 1 2 0 2 SR0 (:38)
- 3 - C 21 DFFE + 0 2 1 1 BR7 (:39)
- 2 - C 22 DFFE + 0 2 1 1 BR6 (:40)
- 6 - A 20 DFFE + 0 2 1 1 BR5 (:41)
- 1 - A 20 DFFE + 0 2 1 1 BR4 (:42)
- 3 - C 19 DFFE + 0 2 1 1 BR3 (:43)
- 1 - C 19 DFFE + 0 2 1 1 BR2 (:44)
- 8 - A 18 DFFE + 0 2 1 1 BR1 (:45)
- 1 - A 18 DFFE + 0 2 1 1 BR0 (:46)
- 3 - A 18 OR2 s 1 2 0 8 ~373~1
- 8 - C 22 AND2 s 4 0 0 17 ~577~1
- 4 - C 22 OR2 1 3 1 0 :691
- 7 - C 22 AND2 1 2 0 1 :693
- 4 - A 18 OR2 ! 1 2 0 0 :705
- 1 - C 22 OR2 1 3 1 0 :706
- 3 - C 22 AND2 1 2 0 1 :708
- 4 - A 20 OR2 1 3 1 0 :721
- 7 - A 20 AND2 1 2 0 1 :723
- 2 - A 20 OR2 1 3 1 0 :736
- 3 - A 20 AND2 1 2 0 1 :738
- 5 - C 19 OR2 1 3 1 0 :751
- 6 - C 19 AND2 1 2 0 1 :753
- 7 - C 19 OR2 1 3 1 0 :766
- 2 - C 19 AND2 1 2 0 1 :768
- 7 - A 18 OR2 1 3 1 0 :781
- 2 - A 18 AND2 1 2 0 1 :783
- 6 - A 18 OR2 1 3 1 0 :796
- 2 - A 23 AND2 1 2 0 1 :797
- 6 - C 22 AND2 s 4 0 0 11 ~983~1
- 4 - A 23 AND2 1 1 0 2 :983
- 1 - A 23 AND2 0 2 0 1 :1147
- 5 - A 23 AND2 0 1 1 0 :1296
- 3 - A 23 OR2 ! 0 3 1 0 :1384
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\study\kb\poc.rpt
poc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 0/ 48( 0%) 8/ 48( 16%) 1/16( 6%) 3/16( 18%) 3/16( 18%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 7/ 96( 7%) 0/ 48( 0%) 9/ 48( 18%) 1/16( 6%) 3/16( 18%) 4/16( 25%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\study\kb\poc.rpt
poc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 CLK
Device-Specific Information: d:\study\kb\poc.rpt
poc
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 2 RESET
Device-Specific Information: d:\study\kb\poc.rpt
poc
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
RDY : INPUT;
RESET : INPUT;
RW : INPUT;
-- Node name is ':46' = 'BR0'
-- Equation name is 'BR0', location is LC1_A18, type is buried.
BR0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = D0 & !_LC3_A18
# BR0 & _LC3_A18;
-- Node name is ':45' = 'BR1'
-- Equation name is 'BR1', location is LC8_A18, type is buried.
BR1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = D1 & !_LC3_A18
# BR1 & _LC3_A18;
-- Node name is ':44' = 'BR2'
-- Equation name is 'BR2', location is LC1_C19, type is buried.
BR2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = D2 & !_LC3_A18
# BR2 & _LC3_A18;
-- Node name is ':43' = 'BR3'
-- Equation name is 'BR3', location is LC3_C19, type is buried.
BR3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = D3 & !_LC3_A18
# BR3 & _LC3_A18;
-- Node name is ':42' = 'BR4'
-- Equation name is 'BR4', location is LC1_A20, type is buried.
BR4 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = D4 & !_LC3_A18
# BR4 & _LC3_A18;
-- Node name is ':41' = 'BR5'
-- Equation name is 'BR5', location is LC6_A20, type is buried.
BR5 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = D5 & !_LC3_A18
# BR5 & _LC3_A18;
-- Node name is ':40' = 'BR6'
-- Equation name is 'BR6', location is LC2_C22, type is buried.
BR6 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = D6 & !_LC3_A18
# BR6 & _LC3_A18;
-- Node name is ':39' = 'BR7'
-- Equation name is 'BR7', location is LC3_C21, type is buried.
BR7 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = D7 & !_LC3_A18
# BR7 & _LC3_A18;
-- Node name is ':28' = 'CURRENT_STATE0'
-- Equation name is 'CURRENT_STATE0', location is LC6_A23, type is buried.
!CURRENT_STATE0 = CURRENT_STATE0~NOT;
CURRENT_STATE0~NOT = DFFE( _EQ009, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ009 = CURRENT_STATE1
# _LC4_A23 & !RDY
# !CURRENT_STATE0 & !RDY
# CURRENT_STATE0 & _LC4_A23;
-- Node name is ':27' = 'CURRENT_STATE1'
-- Equation name is 'CURRENT_STATE1', location is LC8_A23, type is buried.
CURRENT_STATE1 = DFFE( _EQ010, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ010 = CURRENT_STATE1 & !RDY
# CURRENT_STATE0 & !CURRENT_STATE1 & _LC4_A23;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(_LC6_A18, !_LC4_A18);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC7_A18, !_LC4_A18);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(_LC7_C19, !_LC4_A18);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(_LC5_C19, !_LC4_A18);
-- Node name is 'D4'
-- Equation name is 'D4', type is bidir
D4 = TRI(_LC2_A20, !_LC4_A18);
-- Node name is 'D5'
-- Equation name is 'D5', type is bidir
D5 = TRI(_LC4_A20, !_LC4_A18);
-- Node name is 'D6'
-- Equation name is 'D6', type is bidir
D6 = TRI(_LC1_C22, !_LC4_A18);
-- Node name is 'D7'
-- Equation name is 'D7', type is bidir
D7 = TRI(_LC4_C22, !_LC4_A18);
-- Node name is 'IRQ'
-- Equation name is 'IRQ', type is output
IRQ = !_LC3_A23;
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = TRI(BR0, !_LC1_A23);
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = TRI(BR1, !_LC1_A23);
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = TRI(BR2, !_LC1_A23);
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = TRI(BR3, !_LC1_A23);
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = TRI(BR4, !_LC1_A23);
-- Node name is 'PD5'
-- Equation name is 'PD5', type is output
PD5 = TRI(BR5, !_LC1_A23);
-- Node name is 'PD6'
-- Equation name is 'PD6', type is output
PD6 = TRI(BR6, !_LC1_A23);
-- Node name is 'PD7'
-- Equation name is 'PD7', type is output
PD7 = TRI(BR7, !_LC1_A23);
-- Node name is ':38' = 'SR0'
-- Equation name is 'SR0', location is LC7_A23, type is buried.
SR0 = DFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = D0 & _LC8_C22 & RW
# !RW & SR0
# !_LC8_C22 & SR0;
-- Node name is ':37' = 'SR1'
-- Equation name is 'SR1', location is LC5_A18, type is buried.
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