📄 led.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity led is
port(
key_code: in std_logic_vector(7 downto 0);
display: out std_logic_vector(7 downto 0);
seg: out std_logic_vector(1 downto 0)
);
end led;
architecture rtl of led is
signal code: std_logic_vector(3 downto 0);
begin
code <= key_code(3) & key_code(2) & key_code(1) & key_code(0);
process(code)
begin
case (code) is
when "0000" =>
display <="00000011";
when "0001"=>
display <="10011111";
when "0010"=>
display<="00100101";
when "0011"=>
display<="00001101";
when "0100"=>
display<="10011001";
when "0101"=>
display<="01001001";
when "0110"=>
display<="01000001";
when "0111"=>
display<="00011111";
when "1000"=>
display<="00000001";
when "1001"=>
display<="00001001";
when "1010"=>
display<="10011111";
when "1011"=>
display<="00100101";
when "1100"=>
display<="00001101";
when "1101"=>
display<="10011001";
when "1110"=>
display<="01001001";
when "1111"=>
display<="01001001";
when others=>display<="11111111";
end case;
end process;
process(code)
begin
if(code(3)='1') then
if((code(2)) or (code(1))) then
seg<="10";
else
seg<="01";
end if;
else
seg<="01";
end if;
end process;
end;
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