prev_cmp_keyboard.tan.qmsg

矩阵键盘的vhdl编程,非常的实用,带有去抖动

{ "Info" "ITDB_FULL_TCO_RESULT" "clk display\[7\] codetran:u4\|key_code\[0\] 10.991 ns register " "Info: tco from clock \"clk\" to destination pin \"display\[7\]\" through register \"codetran:u4\|key_code\[0\]\" is 10.991 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns codetran:u4\|key_code\[0\] 2 REG LC_X4_Y3_N2 7 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y3_N2; Fanout = 7; REG Node = 'codetran:u4\|key_code\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk codetran:u4|key_code[0] } "NODE_NAME" } } { "codetran.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/codetran.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk codetran:u4|key_code[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout codetran:u4|key_code[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "codetran.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/codetran.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.267 ns + Longest register pin " "Info: + Longest register to pin delay is 7.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns codetran:u4\|key_code\[0\] 1 REG LC_X4_Y3_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N2; Fanout = 7; REG Node = 'codetran:u4\|key_code\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { codetran:u4|key_code[0] } "NODE_NAME" } } { "codetran.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/codetran.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.008 ns) + CELL(0.200 ns) 3.208 ns led:u5\|Mux0~13 2 COMB LC_X3_Y1_N2 1 " "Info: 2: + IC(3.008 ns) + CELL(0.200 ns) = 3.208 ns; Loc. = LC_X3_Y1_N2; Fanout = 1; COMB Node = 'led:u5\|Mux0~13'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.208 ns" { codetran:u4|key_code[0] led:u5|Mux0~13 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(2.322 ns) 7.267 ns display\[7\] 3 PIN PIN_19 0 " "Info: 3: + IC(1.737 ns) + CELL(2.322 ns) = 7.267 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'display\[7\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.059 ns" { led:u5|Mux0~13 display[7] } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.522 ns ( 34.70 % ) " "Info: Total cell delay = 2.522 ns ( 34.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.745 ns ( 65.30 % ) " "Info: Total interconnect delay = 4.745 ns ( 65.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.267 ns" { codetran:u4|key_code[0] led:u5|Mux0~13 display[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.267 ns" { codetran:u4|key_code[0] led:u5|Mux0~13 display[7] } { 0.000ns 3.008ns 1.737ns } { 0.000ns 0.200ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk codetran:u4|key_code[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout codetran:u4|key_code[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.267 ns" { codetran:u4|key_code[0] led:u5|Mux0~13 display[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.267 ns" { codetran:u4|key_code[0] led:u5|Mux0~13 display[7] } { 0.000ns 3.008ns 1.737ns } { 0.000ns 0.200ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "key_press:u2\|sig_2 row\[1\] clk 1.583 ns register " "Info: th for register \"key_press:u2\|sig_2\" (data pin = \"row\[1\]\", clock pin = \"clk\") is 1.583 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.411 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.411 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns scan_gen:u1\|fredivn:u1\|outclk 2 REG LC_X2_Y3_N9 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; REG Node = 'scan_gen:u1\|fredivn:u1\|outclk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk scan_gen:u1|fredivn:u1|outclk } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.769 ns) + CELL(0.918 ns) 7.411 ns key_press:u2\|sig_2 3 REG LC_X4_Y3_N0 2 " "Info: 3: + IC(2.769 ns) + CELL(0.918 ns) = 7.411 ns; Loc. = LC_X4_Y3_N0; Fanout = 2; REG Node = 'key_press:u2\|sig_2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.687 ns" { scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.54 % ) " "Info: Total cell delay = 3.375 ns ( 45.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.036 ns ( 54.46 % ) " "Info: Total interconnect delay = 4.036 ns ( 54.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.049 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns row\[1\] 1 PIN PIN_8 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_8; Fanout = 2; PIN Node = 'row\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { row[1] } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.532 ns) + CELL(0.740 ns) 4.404 ns key_scan:u3\|tmp_1~33 2 COMB LC_X4_Y3_N4 6 " "Info: 2: + IC(2.532 ns) + CELL(0.740 ns) = 4.404 ns; Loc. = LC_X4_Y3_N4; Fanout = 6; COMB Node = 'key_scan:u3\|tmp_1~33'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.272 ns" { row[1] key_scan:u3|tmp_1~33 } "NODE_NAME" } } { "key_scan.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_scan.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.841 ns) + CELL(0.804 ns) 6.049 ns key_press:u2\|sig_2 3 REG LC_X4_Y3_N0 2 " "Info: 3: + IC(0.841 ns) + CELL(0.804 ns) = 6.049 ns; Loc. = LC_X4_Y3_N0; Fanout = 2; REG Node = 'key_press:u2\|sig_2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.645 ns" { key_scan:u3|tmp_1~33 key_press:u2|sig_2 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.676 ns ( 44.24 % ) " "Info: Total cell delay = 2.676 ns ( 44.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.373 ns ( 55.76 % ) " "Info: Total interconnect delay = 3.373 ns ( 55.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.049 ns" { row[1] key_scan:u3|tmp_1~33 key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.049 ns" { row[1] row[1]~combout key_scan:u3|tmp_1~33 key_press:u2|sig_2 } { 0.000ns 0.000ns 2.532ns 0.841ns } { 0.000ns 1.132ns 0.740ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.049 ns" { row[1] key_scan:u3|tmp_1~33 key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.049 ns" { row[1] row[1]~combout key_scan:u3|tmp_1~33 key_press:u2|sig_2 } { 0.000ns 0.000ns 2.532ns 0.841ns } { 0.000ns 1.132ns 0.740ns 0.804ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 5 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 22 17:22:05 2007 " "Info: Processing ended: Thu Nov 22 17:22:05 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}