prev_cmp_keyboard.tan.qmsg

矩阵键盘的vhdl编程,非常的实用,带有去抖动

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register key_press:u2\|sig_3 register key_press:u2\|sig_2 84.72 MHz 11.804 ns Internal " "Info: Clock \"clk\" has Internal fmax of 84.72 MHz between source register \"key_press:u2\|sig_3\" and destination register \"key_press:u2\|sig_2\" (period= 11.804 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.434 ns + Longest register register " "Info: + Longest register to register delay is 2.434 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_press:u2\|sig_3 1 REG LC_X4_Y4_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N5; Fanout = 5; REG Node = 'key_press:u2\|sig_3'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_press:u2|sig_3 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.843 ns) + CELL(0.591 ns) 2.434 ns key_press:u2\|sig_2 2 REG LC_X4_Y3_N0 2 " "Info: 2: + IC(1.843 ns) + CELL(0.591 ns) = 2.434 ns; Loc. = LC_X4_Y3_N0; Fanout = 2; REG Node = 'key_press:u2\|sig_2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.434 ns" { key_press:u2|sig_3 key_press:u2|sig_2 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 24.28 % ) " "Info: Total cell delay = 0.591 ns ( 24.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.843 ns ( 75.72 % ) " "Info: Total interconnect delay = 1.843 ns ( 75.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.434 ns" { key_press:u2|sig_3 key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.434 ns" { key_press:u2|sig_3 key_press:u2|sig_2 } { 0.000ns 1.843ns } { 0.000ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.135 ns - Smallest " "Info: - Smallest clock skew is -3.135 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.411 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.411 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns scan_gen:u1\|fredivn:u1\|outclk 2 REG LC_X2_Y3_N9 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; REG Node = 'scan_gen:u1\|fredivn:u1\|outclk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk scan_gen:u1|fredivn:u1|outclk } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.769 ns) + CELL(0.918 ns) 7.411 ns key_press:u2\|sig_2 3 REG LC_X4_Y3_N0 2 " "Info: 3: + IC(2.769 ns) + CELL(0.918 ns) = 7.411 ns; Loc. = LC_X4_Y3_N0; Fanout = 2; REG Node = 'key_press:u2\|sig_2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.687 ns" { scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.54 % ) " "Info: Total cell delay = 3.375 ns ( 45.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.036 ns ( 54.46 % ) " "Info: Total interconnect delay = 4.036 ns ( 54.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.546 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.546 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns scan_gen:u1\|fredivn:u1\|outclk 2 REG LC_X2_Y3_N9 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; REG Node = 'scan_gen:u1\|fredivn:u1\|outclk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk scan_gen:u1|fredivn:u1|outclk } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.769 ns) + CELL(1.294 ns) 7.787 ns key_press:u2\|sig_2 3 REG LC_X4_Y3_N0 2 " "Info: 3: + IC(2.769 ns) + CELL(1.294 ns) = 7.787 ns; Loc. = LC_X4_Y3_N0; Fanout = 2; REG Node = 'key_press:u2\|sig_2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.063 ns" { scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.019 ns) + CELL(0.740 ns) 10.546 ns key_press:u2\|sig_3 4 REG LC_X4_Y4_N5 5 " "Info: 4: + IC(2.019 ns) + CELL(0.740 ns) = 10.546 ns; Loc. = LC_X4_Y4_N5; Fanout = 5; REG Node = 'key_press:u2\|sig_3'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.759 ns" { key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.491 ns ( 42.58 % ) " "Info: Total cell delay = 4.491 ns ( 42.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.055 ns ( 57.42 % ) " "Info: Total interconnect delay = 6.055 ns ( 57.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.546 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.546 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } { 0.000ns 0.000ns 1.267ns 2.769ns 2.019ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.546 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.546 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } { 0.000ns 0.000ns 1.267ns 2.769ns 2.019ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.434 ns" { key_press:u2|sig_3 key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.434 ns" { key_press:u2|sig_3 key_press:u2|sig_2 } { 0.000ns 1.843ns } { 0.000ns 0.591ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.546 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.546 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } { 0.000ns 0.000ns 1.267ns 2.769ns 2.019ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 3 " "Warning: Circuit may not operate. Detected 3 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "key_press:u2\|counter\[1\] key_press:u2\|sig_3 clk 653 ps " "Info: Found hold time violation between source  pin or register \"key_press:u2\|counter\[1\]\" and destination pin or register \"key_press:u2\|sig_3\" for clock \"clk\" (Hold time is 653 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.135 ns + Largest " "Info: + Largest clock skew is 3.135 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.546 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 10.546 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns scan_gen:u1\|fredivn:u1\|outclk 2 REG LC_X2_Y3_N9 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; REG Node = 'scan_gen:u1\|fredivn:u1\|outclk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk scan_gen:u1|fredivn:u1|outclk } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.769 ns) + CELL(1.294 ns) 7.787 ns key_press:u2\|sig_2 3 REG LC_X4_Y3_N0 2 " "Info: 3: + IC(2.769 ns) + CELL(1.294 ns) = 7.787 ns; Loc. = LC_X4_Y3_N0; Fanout = 2; REG Node = 'key_press:u2\|sig_2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.063 ns" { scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.019 ns) + CELL(0.740 ns) 10.546 ns key_press:u2\|sig_3 4 REG LC_X4_Y4_N5 5 " "Info: 4: + IC(2.019 ns) + CELL(0.740 ns) = 10.546 ns; Loc. = LC_X4_Y4_N5; Fanout = 5; REG Node = 'key_press:u2\|sig_3'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.759 ns" { key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.491 ns ( 42.58 % ) " "Info: Total cell delay = 4.491 ns ( 42.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.055 ns ( 57.42 % ) " "Info: Total interconnect delay = 6.055 ns ( 57.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.546 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.546 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } { 0.000ns 0.000ns 1.267ns 2.769ns 2.019ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.411 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.411 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns scan_gen:u1\|fredivn:u1\|outclk 2 REG LC_X2_Y3_N9 6 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; REG Node = 'scan_gen:u1\|fredivn:u1\|outclk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk scan_gen:u1|fredivn:u1|outclk } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.769 ns) + CELL(0.918 ns) 7.411 ns key_press:u2\|counter\[1\] 3 REG LC_X4_Y4_N3 4 " "Info: 3: + IC(2.769 ns) + CELL(0.918 ns) = 7.411 ns; Loc. = LC_X4_Y4_N3; Fanout = 4; REG Node = 'key_press:u2\|counter\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.687 ns" { scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[1] } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.54 % ) " "Info: Total cell delay = 3.375 ns ( 45.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.036 ns ( 54.46 % ) " "Info: Total interconnect delay = 4.036 ns ( 54.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[1] } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.546 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.546 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } { 0.000ns 0.000ns 1.267ns 2.769ns 2.019ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[1] } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.106 ns - Shortest register register " "Info: - Shortest register to register delay is 2.106 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_press:u2\|counter\[1\] 1 REG LC_X4_Y4_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N3; Fanout = 4; REG Node = 'key_press:u2\|counter\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_press:u2|counter[1] } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.972 ns) + CELL(0.200 ns) 1.172 ns key_press:u2\|key_pre 2 COMB LC_X4_Y4_N1 2 " "Info: 2: + IC(0.972 ns) + CELL(0.200 ns) = 1.172 ns; Loc. = LC_X4_Y4_N1; Fanout = 2; COMB Node = 'key_press:u2\|key_pre'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.172 ns" { key_press:u2|counter[1] key_press:u2|key_pre } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.200 ns) 2.106 ns key_press:u2\|sig_3 3 REG LC_X4_Y4_N5 5 " "Info: 3: + IC(0.734 ns) + CELL(0.200 ns) = 2.106 ns; Loc. = LC_X4_Y4_N5; Fanout = 5; REG Node = 'key_press:u2\|sig_3'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.934 ns" { key_press:u2|key_pre key_press:u2|sig_3 } "NODE_NAME" } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns ( 18.99 % ) " "Info: Total cell delay = 0.400 ns ( 18.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.706 ns ( 81.01 % ) " "Info: Total interconnect delay = 1.706 ns ( 81.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.106 ns" { key_press:u2|counter[1] key_press:u2|key_pre key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.106 ns" { key_press:u2|counter[1] key_press:u2|key_pre key_press:u2|sig_3 } { 0.000ns 0.972ns 0.734ns } { 0.000ns 0.200ns 0.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } } { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.546 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.546 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|sig_2 key_press:u2|sig_3 } { 0.000ns 0.000ns 1.267ns 2.769ns 2.019ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.411 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.411 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[1] } { 0.000ns 0.000ns 1.267ns 2.769ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.106 ns" { key_press:u2|counter[1] key_press:u2|key_pre key_press:u2|sig_3 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.106 ns" { key_press:u2|counter[1] key_press:u2|key_pre key_press:u2|sig_3 } { 0.000ns 0.972ns 0.734ns } { 0.000ns 0.200ns 0.200ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "key_scan:u3\|scan_code\[3\] row\[2\] clk 3.605 ns register " "Info: tsu for register \"key_scan:u3\|scan_code\[3\]\" (data pin = \"row\[2\]\", clock pin = \"clk\") is 3.605 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.620 ns + Longest pin register " "Info: + Longest pin to register delay is 6.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns row\[2\] 1 PIN PIN_12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 2; PIN Node = 'row\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { row[2] } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.298 ns) + CELL(0.511 ns) 4.972 ns key_scan:u3\|tmp_1~33 2 COMB LC_X4_Y3_N4 6 " "Info: 2: + IC(3.298 ns) + CELL(0.511 ns) = 4.972 ns; Loc. = LC_X4_Y3_N4; Fanout = 6; COMB Node = 'key_scan:u3\|tmp_1~33'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.809 ns" { row[2] key_scan:u3|tmp_1~33 } "NODE_NAME" } } { "key_scan.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_scan.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.804 ns) 6.620 ns key_scan:u3\|scan_code\[3\] 3 REG LC_X4_Y3_N5 3 " "Info: 3: + IC(0.844 ns) + CELL(0.804 ns) = 6.620 ns; Loc. = LC_X4_Y3_N5; Fanout = 3; REG Node = 'key_scan:u3\|scan_code\[3\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.648 ns" { key_scan:u3|tmp_1~33 key_scan:u3|scan_code[3] } "NODE_NAME" } } { "key_scan.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_scan.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.478 ns ( 37.43 % ) " "Info: Total cell delay = 2.478 ns ( 37.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.142 ns ( 62.57 % ) " "Info: Total interconnect delay = 4.142 ns ( 62.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.620 ns" { row[2] key_scan:u3|tmp_1~33 key_scan:u3|scan_code[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.620 ns" { row[2] row[2]~combout key_scan:u3|tmp_1~33 key_scan:u3|scan_code[3] } { 0.000ns 0.000ns 3.298ns 0.844ns } { 0.000ns 1.163ns 0.511ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "key_scan.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_scan.vhd" 85 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns key_scan:u3\|scan_code\[3\] 2 REG LC_X4_Y3_N5 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y3_N5; Fanout = 3; REG Node = 'key_scan:u3\|scan_code\[3\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk key_scan:u3|scan_code[3] } "NODE_NAME" } } { "key_scan.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_scan.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_scan:u3|scan_code[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_scan:u3|scan_code[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.620 ns" { row[2] key_scan:u3|tmp_1~33 key_scan:u3|scan_code[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.620 ns" { row[2] row[2]~combout key_scan:u3|tmp_1~33 key_scan:u3|scan_code[3] } { 0.000ns 0.000ns 3.298ns 0.844ns } { 0.000ns 1.163ns 0.511ns 0.804ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_scan:u3|scan_code[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_scan:u3|scan_code[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}