prev_cmp_keyboard.tan.qmsg

矩阵键盘的vhdl编程,非常的实用,带有去抖动

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "key_press:u2\|sig_3 " "Warning: Node \"key_press:u2\|sig_3\" is a latch" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 6 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[1\] " "Info: Detected ripple clock \"key_press:u2\|counter\[1\]\" as buffer" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[0\] " "Info: Detected ripple clock \"key_press:u2\|counter\[0\]\" as buffer" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|sig_2 " "Info: Detected ripple clock \"key_press:u2\|sig_2\" as buffer" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 12 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_press:u2\|sig_2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "scan_gen:u1\|fredivn:u1\|outclk " "Info: Detected ripple clock \"scan_gen:u1\|fredivn:u1\|outclk\" as buffer" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 10 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|outclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[2\] " "Info: Detected ripple clock \"key_press:u2\|counter\[2\]\" as buffer" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[3\] " "Info: Detected ripple clock \"key_press:u2\|counter\[3\]\" as buffer" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "key_press:u2\|key_pre " "Info: Detected gated clock \"key_press:u2\|key_pre\" as buffer" {  } { { "key_press.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_press.vhd" 8 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_press:u2\|key_pre" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}