keyboard.tan.qmsg

矩阵键盘的vhdl编程,非常的实用,带有去抖动

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "key_press:u2\|sig_3 " "Warning: Node \"key_press:u2\|sig_3\" is a latch" {  } { { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "keyboard.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/keyboard.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|sig_2 " "Info: Detected ripple clock \"key_press:u2\|sig_2\" as buffer" {  } { { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 12 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_press:u2\|sig_2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[0\] " "Info: Detected ripple clock \"key_press:u2\|counter\[0\]\" as buffer" {  } { { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[1\] " "Info: Detected ripple clock \"key_press:u2\|counter\[1\]\" as buffer" {  } { { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "scan_gen:u1\|fredivn:u1\|outclk " "Info: Detected ripple clock \"scan_gen:u1\|fredivn:u1\|outclk\" as buffer" {  } { { "fredivn.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/fredivn.vhd" 10 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|outclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[2\] " "Info: Detected ripple clock \"key_press:u2\|counter\[2\]\" as buffer" {  } { { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "key_press:u2\|counter\[3\] " "Info: Detected ripple clock \"key_press:u2\|counter\[3\]\" as buffer" {  } { { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 20 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_press:u2\|counter\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "key_press:u2\|key_pre " "Info: Detected gated clock \"key_press:u2\|key_pre\" as buffer" {  } { { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "key_press:u2\|key_pre" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register key_scan:u3\|dff2:u1\|q register key_scan:u3\|sig_1 82.82 MHz 12.075 ns Internal " "Info: Clock \"clk\" has Internal fmax of 82.82 MHz between source register \"key_scan:u3\|dff2:u1\|q\" and destination register \"key_scan:u3\|sig_1\" (period= 12.075 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.883 ns + Longest register register " "Info: + Longest register to register delay is 1.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_scan:u3\|dff2:u1\|q 1 REG LC_X3_Y2_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N1; Fanout = 1; REG Node = 'key_scan:u3\|dff2:u1\|q'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_scan:u3|dff2:u1|q } "NODE_NAME" } } { "dff2.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/dff2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.292 ns) + CELL(0.591 ns) 1.883 ns key_scan:u3\|sig_1 2 REG LC_X2_Y2_N5 17 " "Info: 2: + IC(1.292 ns) + CELL(0.591 ns) = 1.883 ns; Loc. = LC_X2_Y2_N5; Fanout = 17; REG Node = 'key_scan:u3\|sig_1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.883 ns" { key_scan:u3|dff2:u1|q key_scan:u3|sig_1 } "NODE_NAME" } } { "key_scan.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_scan.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 31.39 % ) " "Info: Total cell delay = 0.591 ns ( 31.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.292 ns ( 68.61 % ) " "Info: Total interconnect delay = 1.292 ns ( 68.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.883 ns" { key_scan:u3|dff2:u1|q key_scan:u3|sig_1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.883 ns" { key_scan:u3|dff2:u1|q key_scan:u3|sig_1 } { 0.000ns 1.292ns } { 0.000ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.483 ns - Smallest " "Info: - Smallest clock skew is -9.483 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.458 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_62 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns key_scan:u3\|sig_1 2 REG LC_X2_Y2_N5 17 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X2_Y2_N5; Fanout = 17; REG Node = 'key_scan:u3\|sig_1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.295 ns" { clk key_scan:u3|sig_1 } "NODE_NAME" } } { "key_scan.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_scan.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.458 ns" { clk key_scan:u3|sig_1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.458 ns" { clk clk~combout key_scan:u3|sig_1 } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.941 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_62 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns scan_gen:u1\|fredivn:u1\|outclk 2 REG LC_X6_Y3_N8 6 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X6_Y3_N8; Fanout = 6; REG Node = 'scan_gen:u1\|fredivn:u1\|outclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.671 ns" { clk scan_gen:u1|fredivn:u1|outclk } "NODE_NAME" } } { "fredivn.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/fredivn.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.321 ns) + CELL(1.294 ns) 8.449 ns key_press:u2\|counter\[0\] 3 REG LC_X3_Y1_N1 5 " "Info: 3: + IC(3.321 ns) + CELL(1.294 ns) = 8.449 ns; Loc. = LC_X3_Y1_N1; Fanout = 5; REG Node = 'key_press:u2\|counter\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.615 ns" { scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[0] } "NODE_NAME" } } { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.987 ns) + CELL(0.914 ns) 11.350 ns key_press:u2\|key_pre 4 COMB LC_X3_Y2_N5 2 " "Info: 4: + IC(1.987 ns) + CELL(0.914 ns) = 11.350 ns; Loc. = LC_X3_Y2_N5; Fanout = 2; COMB Node = 'key_press:u2\|key_pre'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.901 ns" { key_press:u2|counter[0] key_press:u2|key_pre } "NODE_NAME" } } { "key_press.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_press.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.918 ns) 12.941 ns key_scan:u3\|dff2:u1\|q 5 REG LC_X3_Y2_N1 1 " "Info: 5: + IC(0.673 ns) + CELL(0.918 ns) = 12.941 ns; Loc. = LC_X3_Y2_N1; Fanout = 1; REG Node = 'key_scan:u3\|dff2:u1\|q'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.591 ns" { key_press:u2|key_pre key_scan:u3|dff2:u1|q } "NODE_NAME" } } { "dff2.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/dff2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.583 ns ( 43.14 % ) " "Info: Total cell delay = 5.583 ns ( 43.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.358 ns ( 56.86 % ) " "Info: Total interconnect delay = 7.358 ns ( 56.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.941 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[0] key_press:u2|key_pre key_scan:u3|dff2:u1|q } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.941 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[0] key_press:u2|key_pre key_scan:u3|dff2:u1|q } { 0.000ns 0.000ns 1.377ns 3.321ns 1.987ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.458 ns" { clk key_scan:u3|sig_1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.458 ns" { clk clk~combout key_scan:u3|sig_1 } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.941 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[0] key_press:u2|key_pre key_scan:u3|dff2:u1|q } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.941 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[0] key_press:u2|key_pre key_scan:u3|dff2:u1|q } { 0.000ns 0.000ns 1.377ns 3.321ns 1.987ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "dff2.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/dff2.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "key_scan.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_scan.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.883 ns" { key_scan:u3|dff2:u1|q key_scan:u3|sig_1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.883 ns" { key_scan:u3|dff2:u1|q key_scan:u3|sig_1 } { 0.000ns 1.292ns } { 0.000ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.458 ns" { clk key_scan:u3|sig_1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.458 ns" { clk clk~combout key_scan:u3|sig_1 } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.941 ns" { clk scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[0] key_press:u2|key_pre key_scan:u3|dff2:u1|q } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.941 ns" { clk clk~combout scan_gen:u1|fredivn:u1|outclk key_press:u2|counter[0] key_press:u2|key_pre key_scan:u3|dff2:u1|q } { 0.000ns 0.000ns 1.377ns 3.321ns 1.987ns 0.673ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.914ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "key_scan:u3\|scan_code\[2\] row\[3\] clk 2.912 ns register " "Info: tsu for register \"key_scan:u3\|scan_code\[2\]\" (data pin = \"row\[3\]\", clock pin = \"clk\") is 2.912 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.037 ns + Longest pin register " "Info: + Longest pin to register delay is 6.037 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns row\[3\] 1 PIN PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_37; Fanout = 2; PIN Node = 'row\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { row[3] } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/keyboard.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.618 ns) + CELL(0.914 ns) 4.664 ns key_scan:u3\|tmp_1~27 2 COMB LC_X3_Y1_N3 6 " "Info: 2: + IC(2.618 ns) + CELL(0.914 ns) = 4.664 ns; Loc. = LC_X3_Y1_N3; Fanout = 6; COMB Node = 'key_scan:u3\|tmp_1~27'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.532 ns" { row[3] key_scan:u3|tmp_1~27 } "NODE_NAME" } } { "key_scan.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_scan.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.591 ns) 6.037 ns key_scan:u3\|scan_code\[2\] 3 REG LC_X3_Y1_N6 3 " "Info: 3: + IC(0.782 ns) + CELL(0.591 ns) = 6.037 ns; Loc. = LC_X3_Y1_N6; Fanout = 3; REG Node = 'key_scan:u3\|scan_code\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.373 ns" { key_scan:u3|tmp_1~27 key_scan:u3|scan_code[2] } "NODE_NAME" } } { "key_scan.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_scan.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.637 ns ( 43.68 % ) " "Info: Total cell delay = 2.637 ns ( 43.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns ( 56.32 % ) " "Info: Total interconnect delay = 3.400 ns ( 56.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.037 ns" { row[3] key_scan:u3|tmp_1~27 key_scan:u3|scan_code[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.037 ns" { row[3] row[3]~combout key_scan:u3|tmp_1~27 key_scan:u3|scan_code[2] } { 0.000ns 0.000ns 2.618ns 0.782ns } { 0.000ns 1.132ns 0.914ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "key_scan.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_scan.vhd" 85 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.458 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_62 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/keyboard.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns key_scan:u3\|scan_code\[2\] 2 REG LC_X3_Y1_N6 3 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X3_Y1_N6; Fanout = 3; REG Node = 'key_scan:u3\|scan_code\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.295 ns" { clk key_scan:u3|scan_code[2] } "NODE_NAME" } } { "key_scan.vhd" "" { Text "C:/Documents and Settings/xiazi/桌面/代码/keyboard/keyboard/key_scan.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.458 ns" { clk key_scan:u3|scan_code[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.458 ns" { clk clk~combout key_scan:u3|scan_code[2] } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.037 ns" { row[3] key_scan:u3|tmp_1~27 key_scan:u3|scan_code[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.037 ns" { row[3] row[3]~combout key_scan:u3|tmp_1~27 key_scan:u3|scan_code[2] } { 0.000ns 0.000ns 2.618ns 0.782ns } { 0.000ns 1.132ns 0.914ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.458 ns" { clk key_scan:u3|scan_code[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.458 ns" { clk clk~combout key_scan:u3|scan_code[2] } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}