prev_cmp_keyboard.fit.qmsg

矩阵键盘的vhdl编程,非常的实用,带有去抖动

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.489 ns register register " "Info: Estimated most critical path is register to register delay of 10.489 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_gen:u1\|fredivn:u1\|count\[27\] 1 REG LAB_X6_Y1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y1; Fanout = 4; REG Node = 'scan_gen:u1\|fredivn:u1\|count\[27\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[27] } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.327 ns) + CELL(0.200 ns) 2.527 ns scan_gen:u1\|fredivn:u1\|Equal0~288 2 COMB LAB_X6_Y2 1 " "Info: 2: + IC(2.327 ns) + CELL(0.200 ns) = 2.527 ns; Loc. = LAB_X6_Y2; Fanout = 1; COMB Node = 'scan_gen:u1\|fredivn:u1\|Equal0~288'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.527 ns" { scan_gen:u1|fredivn:u1|count[27] scan_gen:u1|fredivn:u1|Equal0~288 } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.914 ns) 4.801 ns scan_gen:u1\|fredivn:u1\|Equal0~292 3 COMB LAB_X6_Y3 1 " "Info: 3: + IC(1.360 ns) + CELL(0.914 ns) = 4.801 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'scan_gen:u1\|fredivn:u1\|Equal0~292'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.274 ns" { scan_gen:u1|fredivn:u1|Equal0~288 scan_gen:u1|fredivn:u1|Equal0~292 } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.914 ns) 6.057 ns scan_gen:u1\|fredivn:u1\|Equal0~293 4 COMB LAB_X6_Y3 2 " "Info: 4: + IC(0.342 ns) + CELL(0.914 ns) = 6.057 ns; Loc. = LAB_X6_Y3; Fanout = 2; COMB Node = 'scan_gen:u1\|fredivn:u1\|Equal0~293'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.256 ns" { scan_gen:u1|fredivn:u1|Equal0~292 scan_gen:u1|fredivn:u1|Equal0~293 } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 7.237 ns scan_gen:u1\|fredivn:u1\|Equal0~298 5 COMB LAB_X6_Y3 8 " "Info: 5: + IC(0.266 ns) + CELL(0.914 ns) = 7.237 ns; Loc. = LAB_X6_Y3; Fanout = 8; COMB Node = 'scan_gen:u1\|fredivn:u1\|Equal0~298'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { scan_gen:u1|fredivn:u1|Equal0~293 scan_gen:u1|fredivn:u1|Equal0~298 } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.661 ns) + CELL(0.591 ns) 10.489 ns scan_gen:u1\|fredivn:u1\|count\[10\] 6 REG LAB_X2_Y2 4 " "Info: 6: + IC(2.661 ns) + CELL(0.591 ns) = 10.489 ns; Loc. = LAB_X2_Y2; Fanout = 4; REG Node = 'scan_gen:u1\|fredivn:u1\|count\[10\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.252 ns" { scan_gen:u1|fredivn:u1|Equal0~298 scan_gen:u1|fredivn:u1|count[10] } "NODE_NAME" } } { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.533 ns ( 33.68 % ) " "Info: Total cell delay = 3.533 ns ( 33.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.956 ns ( 66.32 % ) " "Info: Total interconnect delay = 6.956 ns ( 66.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.489 ns" { scan_gen:u1|fredivn:u1|count[27] scan_gen:u1|fredivn:u1|Equal0~288 scan_gen:u1|fredivn:u1|Equal0~292 scan_gen:u1|fredivn:u1|Equal0~293 scan_gen:u1|fredivn:u1|Equal0~298 scan_gen:u1|fredivn:u1|count[10] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_VERY_HIGH_HOLD_REQUIREMENTS_DETECTED" "17 294 " "Warning: 17 (of 294) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." { { "Info" "IFITAPI_FITAPI_INFO_VPR_REGISTERS_WITH_VERY_HIGH_HOLD_REQUIREMENTS" "17 " "Info: Found 17 Registers with very high hold time requirements" { { "Info" "IFITAPI_FITAPI_ATOM_NAME" "codetran:u4\|key_code\[1\] " "Info: Node \"codetran:u4\|key_code\[1\]\"" {  } { { "codetran.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/codetran.vhd" 14 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "codetran:u4\|key_code\[1\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { codetran:u4|key_code[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { codetran:u4|key_code[1] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[29\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[29\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[29\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[29] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[29] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[27\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[27\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[27\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[27] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[27] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[25\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[25\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[25\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[25] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[25] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[20\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[20\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[20\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[20] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[20] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[19\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[19\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[19\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[19] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[19] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[17\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[17\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[17\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[17] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[17] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[16\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[16\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[16\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[16] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[16] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[13\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[13\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[13\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[13] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[13] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[12\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[12\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[12\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[12] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[12] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[10\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[10\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[10\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[10] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[2\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[2\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[2\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[2] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[7\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[7\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[7\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[7] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "scan_gen:u1\|fredivn:u1\|count\[21\] " "Info: Node \"scan_gen:u1\|fredivn:u1\|count\[21\]\"" {  } { { "fredivn.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/fredivn.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan_gen:u1\|fredivn:u1\|count\[21\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[21] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan_gen:u1|fredivn:u1|count[21] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "key_scan:u3\|sig_1 " "Info: Node \"key_scan:u3\|sig_1\"" {  } { { "key_scan.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_scan.vhd" 14 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_scan:u3\|sig_1" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_scan:u3|sig_1 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_scan:u3|sig_1 } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "codetran:u4\|key_code\[0\] " "Info: Node \"codetran:u4\|key_code\[0\]\"" {  } { { "codetran.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/codetran.vhd" 14 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "codetran:u4\|key_code\[0\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { codetran:u4|key_code[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { codetran:u4|key_code[0] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "key_scan:u3\|com\[0\] " "Info: Node \"key_scan:u3\|com\[0\]\"" {  } { { "key_scan.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/key_scan.vhd" 44 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_scan:u3\|com\[0\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_scan:u3|com[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_scan:u3|com[0] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Found %1!d! Registers with very high hold time requirements" 0 0 "" 0}  } {  } 0 0 "%1!d! (of %2!d!) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 11 " "Info: Average interconnect usage is 11% of the available device resources. Peak interconnect usage is 11%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "display\[0\] VCC " "Info: Pin display\[0\] has VCC driving its datain port" {  } { { "keyboard.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.vhd" 9 -1 0 } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { display[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { display[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.fit.smsg " "Info: Generated suppressed messages file E:/开发板/资料/代码/CPLD/VHDL/keyboard/keyboard.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "169 " "Info: Allocated 169 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 22 17:21:55 2007 " "Info: Processing ended: Thu Nov 22 17:21:55 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}