uart.tan.qmsg

vhdl书写uart代码,经验证功能非常的全.

{ "Info" "ITDB_TH_RESULT" "shift_register:U_SR\|shift_regs\[0\] reset_n clk 5.829 ns register " "Info: th for register \"shift_register:U_SR\|shift_regs\[0\]\" (data pin = \"reset_n\", clock pin = \"clk\") is 5.829 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.013 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 10.013 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 49 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 49; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns uart_core:U_Core\|sel_clk 2 REG LC_X4_Y4_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y4_N4; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk uart_core:U_Core|sel_clk } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.608 ns) + CELL(0.200 ns) 6.532 ns switch:U_SRClkSwitch\|dout 3 COMB LC_X2_Y3_N8 11 " "Info: 3: + IC(2.608 ns) + CELL(0.200 ns) = 6.532 ns; Loc. = LC_X2_Y3_N8; Fanout = 11; COMB Node = 'switch:U_SRClkSwitch\|dout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.808 ns" { uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout } "NODE_NAME" } } { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.563 ns) + CELL(0.918 ns) 10.013 ns shift_register:U_SR\|shift_regs\[0\] 4 REG LC_X7_Y3_N7 2 " "Info: 4: + IC(2.563 ns) + CELL(0.918 ns) = 10.013 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'shift_register:U_SR\|shift_regs\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.481 ns" { switch:U_SRClkSwitch|dout shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.575 ns ( 35.70 % ) " "Info: Total cell delay = 3.575 ns ( 35.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.438 ns ( 64.30 % ) " "Info: Total interconnect delay = 6.438 ns ( 64.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.013 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.013 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|shift_regs[0] } { 0.000ns 0.000ns 1.267ns 2.608ns 2.563ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.405 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns reset_n 1 PIN PIN_12 28 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 28; PIN Node = 'reset_n'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_n } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.059 ns) + CELL(1.183 ns) 4.405 ns shift_register:U_SR\|shift_regs\[0\] 2 REG LC_X7_Y3_N7 2 " "Info: 2: + IC(2.059 ns) + CELL(1.183 ns) = 4.405 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'shift_register:U_SR\|shift_regs\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.242 ns" { reset_n shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.346 ns ( 53.26 % ) " "Info: Total cell delay = 2.346 ns ( 53.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.059 ns ( 46.74 % ) " "Info: Total interconnect delay = 2.059 ns ( 46.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.405 ns" { reset_n shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.405 ns" { reset_n reset_n~combout shift_register:U_SR|shift_regs[0] } { 0.000ns 0.000ns 2.059ns } { 0.000ns 1.163ns 1.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.013 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.013 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|shift_regs[0] } { 0.000ns 0.000ns 1.267ns 2.608ns 2.563ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.405 ns" { reset_n shift_register:U_SR|shift_regs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.405 ns" { reset_n reset_n~combout shift_register:U_SR|shift_regs[0] } { 0.000ns 0.000ns 2.059ns } { 0.000ns 1.163ns 1.183ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 22 18:00:52 2007 " "Info: Processing ended: Thu Nov 22 18:00:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}