uart.tan.qmsg

vhdl书写uart代码,经验证功能非常的全.

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 47 " "Warning: Circuit may not operate. Detected 47 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "uart_core:U_Core\|ce_parts counter:U_Counter\|count\[11\] clk 2.742 ns " "Info: Found hold time violation between source  pin or register \"uart_core:U_Core\|ce_parts\" and destination pin or register \"counter:U_Counter\|count\[11\]\" for clock \"clk\" (Hold time is 2.742 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.679 ns + Largest " "Info: + Largest clock skew is 6.679 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.027 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 10.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 49 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 49; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns uart_core:U_Core\|sel_clk 2 REG LC_X4_Y4_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y4_N4; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk uart_core:U_Core|sel_clk } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.607 ns) + CELL(0.200 ns) 6.531 ns switch:U_CounterClkSwitch\|dout 3 COMB LC_X2_Y3_N9 33 " "Info: 3: + IC(2.607 ns) + CELL(0.200 ns) = 6.531 ns; Loc. = LC_X2_Y3_N9; Fanout = 33; COMB Node = 'switch:U_CounterClkSwitch\|dout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.807 ns" { uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout } "NODE_NAME" } } { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.578 ns) + CELL(0.918 ns) 10.027 ns counter:U_Counter\|count\[11\] 4 REG LC_X3_Y1_N6 4 " "Info: 4: + IC(2.578 ns) + CELL(0.918 ns) = 10.027 ns; Loc. = LC_X3_Y1_N6; Fanout = 4; REG Node = 'counter:U_Counter\|count\[11\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.496 ns" { switch:U_CounterClkSwitch|dout counter:U_Counter|count[11] } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.575 ns ( 35.65 % ) " "Info: Total cell delay = 3.575 ns ( 35.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.452 ns ( 64.35 % ) " "Info: Total interconnect delay = 6.452 ns ( 64.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.027 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|count[11] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.027 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|count[11] } { 0.000ns 0.000ns 1.267ns 2.607ns 2.578ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 49 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 49; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns uart_core:U_Core\|ce_parts 2 REG LC_X4_Y4_N6 54 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N6; Fanout = 54; REG Node = 'uart_core:U_Core\|ce_parts'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk uart_core:U_Core|ce_parts } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|ce_parts } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|ce_parts } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.027 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|count[11] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.027 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|count[11] } { 0.000ns 0.000ns 1.267ns 2.607ns 2.578ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|ce_parts } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|ce_parts } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.782 ns - Shortest register register " "Info: - Shortest register to register delay is 3.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_core:U_Core\|ce_parts 1 REG LC_X4_Y4_N6 54 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N6; Fanout = 54; REG Node = 'uart_core:U_Core\|ce_parts'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_core:U_Core|ce_parts } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.539 ns) + CELL(1.243 ns) 3.782 ns counter:U_Counter\|count\[11\] 2 REG LC_X3_Y1_N6 4 " "Info: 2: + IC(2.539 ns) + CELL(1.243 ns) = 3.782 ns; Loc. = LC_X3_Y1_N6; Fanout = 4; REG Node = 'counter:U_Counter\|count\[11\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.782 ns" { uart_core:U_Core|ce_parts counter:U_Counter|count[11] } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.243 ns ( 32.87 % ) " "Info: Total cell delay = 1.243 ns ( 32.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.539 ns ( 67.13 % ) " "Info: Total interconnect delay = 2.539 ns ( 67.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.782 ns" { uart_core:U_Core|ce_parts counter:U_Counter|count[11] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.782 ns" { uart_core:U_Core|ce_parts counter:U_Counter|count[11] } { 0.000ns 2.539ns } { 0.000ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.027 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|count[11] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.027 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|count[11] } { 0.000ns 0.000ns 1.267ns 2.607ns 2.578ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|ce_parts } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|ce_parts } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.782 ns" { uart_core:U_Core|ce_parts counter:U_Counter|count[11] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.782 ns" { uart_core:U_Core|ce_parts counter:U_Counter|count[11] } { 0.000ns 2.539ns } { 0.000ns 1.243ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "uart_core:U_Core\|si_count\[2\] send clk 4.327 ns register " "Info: tsu for register \"uart_core:U_Core\|si_count\[2\]\" (data pin = \"send\", clock pin = \"clk\") is 4.327 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.342 ns + Longest pin register " "Info: + Longest pin to register delay is 7.342 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns send 1 PIN PIN_72 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_72; Fanout = 7; PIN Node = 'send'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { send } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.034 ns) + CELL(0.740 ns) 4.906 ns uart_core:U_Core\|state.uart_end_recv~53 2 COMB LC_X7_Y4_N3 2 " "Info: 2: + IC(3.034 ns) + CELL(0.740 ns) = 4.906 ns; Loc. = LC_X7_Y4_N3; Fanout = 2; COMB Node = 'uart_core:U_Core\|state.uart_end_recv~53'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.774 ns" { send uart_core:U_Core|state.uart_end_recv~53 } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.411 ns uart_core:U_Core\|si_count\[3\]~322 3 COMB LC_X7_Y4_N4 4 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 5.411 ns; Loc. = LC_X7_Y4_N4; Fanout = 4; COMB Node = 'uart_core:U_Core\|si_count\[3\]~322'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { uart_core:U_Core|state.uart_end_recv~53 uart_core:U_Core|si_count[3]~322 } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(1.243 ns) 7.342 ns uart_core:U_Core\|si_count\[2\] 4 REG LC_X7_Y4_N2 4 " "Info: 4: + IC(0.688 ns) + CELL(1.243 ns) = 7.342 ns; Loc. = LC_X7_Y4_N2; Fanout = 4; REG Node = 'uart_core:U_Core\|si_count\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.931 ns" { uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.315 ns ( 45.15 % ) " "Info: Total cell delay = 3.315 ns ( 45.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.027 ns ( 54.85 % ) " "Info: Total interconnect delay = 4.027 ns ( 54.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.342 ns" { send uart_core:U_Core|state.uart_end_recv~53 uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.342 ns" { send send~combout uart_core:U_Core|state.uart_end_recv~53 uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 3.034ns 0.305ns 0.688ns } { 0.000ns 1.132ns 0.740ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 49 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 49; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns uart_core:U_Core\|si_count\[2\] 2 REG LC_X7_Y4_N2 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y4_N2; Fanout = 4; REG Node = 'uart_core:U_Core\|si_count\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.342 ns" { send uart_core:U_Core|state.uart_end_recv~53 uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.342 ns" { send send~combout uart_core:U_Core|state.uart_end_recv~53 uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 3.034ns 0.305ns 0.688ns } { 0.000ns 1.132ns 0.740ns 0.200ns 1.243ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk TxD shift_register:U_SR\|dout 13.946 ns register " "Info: tco from clock \"clk\" to destination pin \"TxD\" through register \"shift_register:U_SR\|dout\" is 13.946 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.013 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.013 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 49 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 49; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns uart_core:U_Core\|sel_clk 2 REG LC_X4_Y4_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y4_N4; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk uart_core:U_Core|sel_clk } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.608 ns) + CELL(0.200 ns) 6.532 ns switch:U_SRClkSwitch\|dout 3 COMB LC_X2_Y3_N8 11 " "Info: 3: + IC(2.608 ns) + CELL(0.200 ns) = 6.532 ns; Loc. = LC_X2_Y3_N8; Fanout = 11; COMB Node = 'switch:U_SRClkSwitch\|dout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.808 ns" { uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout } "NODE_NAME" } } { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.563 ns) + CELL(0.918 ns) 10.013 ns shift_register:U_SR\|dout 4 REG LC_X2_Y1_N8 1 " "Info: 4: + IC(2.563 ns) + CELL(0.918 ns) = 10.013 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; REG Node = 'shift_register:U_SR\|dout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.481 ns" { switch:U_SRClkSwitch|dout shift_register:U_SR|dout } "NODE_NAME" } } { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.575 ns ( 35.70 % ) " "Info: Total cell delay = 3.575 ns ( 35.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.438 ns ( 64.30 % ) " "Info: Total interconnect delay = 6.438 ns ( 64.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.013 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|dout } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.013 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|dout } { 0.000ns 0.000ns 1.267ns 2.608ns 2.563ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.557 ns + Longest register pin " "Info: + Longest register to pin delay is 3.557 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_register:U_SR\|dout 1 REG LC_X2_Y1_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; REG Node = 'shift_register:U_SR\|dout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_register:U_SR|dout } "NODE_NAME" } } { "shift_register.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/shift_register.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns switch:U_TXDSwitch\|dout~2 2 COMB LC_X2_Y1_N8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'switch:U_TXDSwitch\|dout~2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 } "NODE_NAME" } } { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.640 ns) + CELL(2.322 ns) 3.557 ns TxD 3 PIN PIN_26 0 " "Info: 3: + IC(0.640 ns) + CELL(2.322 ns) = 3.557 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'TxD'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { switch:U_TXDSwitch|dout~2 TxD } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.917 ns ( 82.01 % ) " "Info: Total cell delay = 2.917 ns ( 82.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.640 ns ( 17.99 % ) " "Info: Total interconnect delay = 0.640 ns ( 17.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.557 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.557 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } { 0.000ns 0.000ns 0.640ns } { 0.000ns 0.595ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.013 ns" { clk uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|dout } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.013 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_SRClkSwitch|dout shift_register:U_SR|dout } { 0.000ns 0.000ns 1.267ns 2.608ns 2.563ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.557 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.557 ns" { shift_register:U_SR|dout switch:U_TXDSwitch|dout~2 TxD } { 0.000ns 0.000ns 0.640ns } { 0.000ns 0.595ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}