uart.tan.qmsg

vhdl书写uart代码,经验证功能非常的全.

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "baudrate_generator:U_BG\|indicator " "Info: Detected ripple clock \"baudrate_generator:U_BG\|indicator\" as buffer" {  } { { "baudrate_generator.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/baudrate_generator.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "baudrate_generator:U_BG\|indicator" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "uart_core:U_Core\|sel_clk " "Info: Detected ripple clock \"uart_core:U_Core\|sel_clk\" as buffer" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 29 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "uart_core:U_Core\|sel_clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "baudrate_generator:U_BG\|bg_out " "Info: Detected ripple clock \"baudrate_generator:U_BG\|bg_out\" as buffer" {  } { { "baudrate_generator.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/baudrate_generator.vhd" 17 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "baudrate_generator:U_BG\|bg_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "switch:U_SRClkSwitch\|dout " "Info: Detected gated clock \"switch:U_SRClkSwitch\|dout\" as buffer" {  } { { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 10 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "switch:U_SRClkSwitch\|dout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "switch:U_CounterClkSwitch\|dout " "Info: Detected gated clock \"switch:U_CounterClkSwitch\|dout\" as buffer" {  } { { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 10 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "switch:U_CounterClkSwitch\|dout" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter:U_Counter\|overflow register uart_core:U_Core\|si_count\[2\] 80.61 MHz 12.405 ns Internal " "Info: Clock \"clk\" has Internal fmax of 80.61 MHz between source register \"counter:U_Counter\|overflow\" and destination register \"uart_core:U_Core\|si_count\[2\]\" (period= 12.405 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.017 ns + Longest register register " "Info: + Longest register to register delay is 5.017 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:U_Counter\|overflow 1 REG LC_X5_Y2_N1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N1; Fanout = 13; REG Node = 'counter:U_Counter\|overflow'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter:U_Counter|overflow } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.575 ns) + CELL(0.511 ns) 3.086 ns uart_core:U_Core\|si_count\[3\]~322 2 COMB LC_X7_Y4_N4 4 " "Info: 2: + IC(2.575 ns) + CELL(0.511 ns) = 3.086 ns; Loc. = LC_X7_Y4_N4; Fanout = 4; COMB Node = 'uart_core:U_Core\|si_count\[3\]~322'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.086 ns" { counter:U_Counter|overflow uart_core:U_Core|si_count[3]~322 } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.688 ns) + CELL(1.243 ns) 5.017 ns uart_core:U_Core\|si_count\[2\] 3 REG LC_X7_Y4_N2 4 " "Info: 3: + IC(0.688 ns) + CELL(1.243 ns) = 5.017 ns; Loc. = LC_X7_Y4_N2; Fanout = 4; REG Node = 'uart_core:U_Core\|si_count\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.931 ns" { uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.754 ns ( 34.96 % ) " "Info: Total cell delay = 1.754 ns ( 34.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.263 ns ( 65.04 % ) " "Info: Total interconnect delay = 3.263 ns ( 65.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.017 ns" { counter:U_Counter|overflow uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.017 ns" { counter:U_Counter|overflow uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } { 0.000ns 2.575ns 0.688ns } { 0.000ns 0.511ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.679 ns - Smallest " "Info: - Smallest clock skew is -6.679 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 49 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 49; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns uart_core:U_Core\|si_count\[2\] 2 REG LC_X7_Y4_N2 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y4_N2; Fanout = 4; REG Node = 'uart_core:U_Core\|si_count\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.027 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 49 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 49; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_top.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_top.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns uart_core:U_Core\|sel_clk 2 REG LC_X4_Y4_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y4_N4; Fanout = 3; REG Node = 'uart_core:U_Core\|sel_clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk uart_core:U_Core|sel_clk } "NODE_NAME" } } { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.607 ns) + CELL(0.200 ns) 6.531 ns switch:U_CounterClkSwitch\|dout 3 COMB LC_X2_Y3_N9 33 " "Info: 3: + IC(2.607 ns) + CELL(0.200 ns) = 6.531 ns; Loc. = LC_X2_Y3_N9; Fanout = 33; COMB Node = 'switch:U_CounterClkSwitch\|dout'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.807 ns" { uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout } "NODE_NAME" } } { "switch.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/switch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.578 ns) + CELL(0.918 ns) 10.027 ns counter:U_Counter\|overflow 4 REG LC_X5_Y2_N1 13 " "Info: 4: + IC(2.578 ns) + CELL(0.918 ns) = 10.027 ns; Loc. = LC_X5_Y2_N1; Fanout = 13; REG Node = 'counter:U_Counter\|overflow'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.496 ns" { switch:U_CounterClkSwitch|dout counter:U_Counter|overflow } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.575 ns ( 35.65 % ) " "Info: Total cell delay = 3.575 ns ( 35.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.452 ns ( 64.35 % ) " "Info: Total interconnect delay = 6.452 ns ( 64.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.027 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|overflow } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.027 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|overflow } { 0.000ns 0.000ns 1.267ns 2.607ns 2.578ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.027 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|overflow } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.027 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|overflow } { 0.000ns 0.000ns 1.267ns 2.607ns 2.578ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "counter.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/counter.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "uart_core.vhd" "" { Text "E:/开发板/资料/代码/CPLD/VHDL/uart/uart_core.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.017 ns" { counter:U_Counter|overflow uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.017 ns" { counter:U_Counter|overflow uart_core:U_Core|si_count[3]~322 uart_core:U_Core|si_count[2] } { 0.000ns 2.575ns 0.688ns } { 0.000ns 0.511ns 1.243ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk uart_core:U_Core|si_count[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout uart_core:U_Core|si_count[2] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.027 ns" { clk uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|overflow } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.027 ns" { clk clk~combout uart_core:U_Core|sel_clk switch:U_CounterClkSwitch|dout counter:U_Counter|overflow } { 0.000ns 0.000ns 1.267ns 2.607ns 2.578ns } { 0.000ns 1.163ns 1.294ns 0.200ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}